Testing and Reliable Design of Cmos Circuits: 88 - Rilegato

Jha, Niraj K.; Kundu, Sandip

Rilegato

ISBN 10: 0792390563 ISBN 13: 9780792390565

Casa editrice: Kluwer Academic Pub, 1989

Riassunto

In the last few years CMOS technology has become increas­ ingly dominant for realizing Very Large Scale Integrated (VLSI) circuits. The popularity of this technology is due to its high den­ sity and low power requirement. The ability to realize very com­ plex circuits on a single chip has brought about a revolution in the world of electronics and computers. However, the rapid advance­ ments in this area pose many new problems in the area of testing. Testing has become a very time-consuming process. In order to ease the burden of testing, many schemes for designing the circuit for improved testability have been presented. These design for testability techniques have begun to catch the attention of chip manufacturers. The trend is towards placing increased emphasis on these techniques. Another byproduct of the increase in the complexity of chips is their higher susceptibility to faults. In order to take care of this problem, we need to build fault-tolerant systems. The area of fault-tolerant computing has steadily gained in importance. Today many universities offer courses in the areas of digital system testing and fault-tolerant computing. Due to the impor­ tance of CMOS technology, a significant portion of these courses may be devoted to CMOS testing. This book has been written as a reference text for such courses offered at the senior or graduate level. Familiarity with logic design and switching theory is assumed. The book should also prove to be useful to professionals working in the semiconductor industry.

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Contenuti

1. Introduction.- 1.1 What is Testing ?.- 1.2 Faults and Errors.- 1.3 Different Types of CMOS Circuits.- 1.3.1 Static CMOS Circuits.- 1.3.2 Dynamic CMOS Circuits.- 1.4 Gate-Level Model.- 1.5 Fault Models.- 1.5.1 Stuck-at Fault Model.- 1.5.2 Stuck-open Fault Model.- 1.5.3 Stuck-on Fault Model.- 1.5.4 Bridging Fault Model.- 1.5.5 Delay Fault Model.- References.- Problems.- 2. Test Invalidation.- 2.1 The Test Invalidation Problem.- 2.1.1 Test Invalidation due to Circuit Delays.- 2.1.2 Test Invalidation due to Charge Sharing.- 2.2 Robust Testability of Dynamic CMOS Circuits.- References.- Additional Reading.- Problems.- 3. Test Generation for Dynamic CMOS Circuits.- 3.1 Path Sensitization and D-Algorithm.- 3.2 Boolean Difference.- 3.3 Fault Collapsing.- 3.4 Redundancy in Circuits.- 3.5 Testing of Domino CMOS Circuits.- 3.5.1 Testing of Gates with Series-Parallel Network.- 3.5.2 Testing of Gates with Non-Series-Parallel Network.- 3.5.3 Testing of a General Circuit.- 3.5.4 Ordering of Test.- 3.6 Testing of CVS Circuits.- References.- Additional Reading.- Problems.- 4. Test Generation for Static CMOS Circuits.- 4.1 Non-Robust Test Generation.- 4.1.1 Test Generation from a Gate-Level Model.- 4.1.1.1 The Jain-Agrawal Method.- 4.1.1.2 The Reddy-Agrawal-Jain Method.- 4.1.1.3 The Chandramouli Method.- 4.1.2 Test Generation at the Switch Level.- 4.1.2.1 The Chiang-Vranesic Method.- 4.1.2.2 The Agrawal-Reddy Method.- 4.1.2.3 The Shih-Abraham Method.- 4.2 Robust Test Generation.- 4.2.1 The Reddy-Reddy-Agrawal Method.- 4.2.2 Some Issues in Robust Test Generation.- References.- Additional Reading.- Problems.- 5. Design for Robust Testability.- 5.1 Testable Designs Using Extra Inputs.- 5.1.1 The Reddy-Reddy-Kuhl Method.- 5.1.2 The Liu-McCluskey Method.- 5.2 Testable Designs Using Complex Gates.- 5.3 Testable Designs Using Parity Gates.- 5.4 Testable Designs Using Shannon’s Theorem.- 5.4.1 Path Delay Faults.- 5.4.2 Robustly Testable Design.- References.- Additional Reading.- Problems.- 6. Self-Checking Circuits.- 6.1 Concepts and Definitions.- 6.2 Error-Detecting Codes.- 6.2.1 Codes for Detecting All Unidirectional Errors.- 6.2.2 t-Unidirectional Error-Detecting Codes.- 6.2.3 t-Burst Unidirectional Error-Detecting Codes.- 6.3 Self-Checking Checkers.- 6.3.1 Static vs Dynamic CMOS Implementations.- 6.3.2 Two-Rail Checkers.- 6.3.3 Parity Checkers.- 6.3.4 m-out-of-n Checkers.- 6.3.5 Berger Checkers.- 6.3.6 Checkers for Borden, Bose-Lin, Bose and Blaum Codes.- 6.3.7 Embedded Checker Problem.- 6.4 Self-Checking Functional Circuits.- References.- Additional Reading.- Problems.- 7. Conclusions.- References.

Product Description

Book by Jha Niraj K Kundu Sandip

Dettagli dell?edizione

• Editore: Kluwer Academic Pub
• Data di pubblicazione: 1989
• Lingua: Inglese
• ISBN 10: 0792390563
• ISBN 13: 9780792390565
• Rilegatura: Copertina rigida
• Numero di pagine: 260
• Contatto del produttore: non disponibile
• Persona responsabile: Springer Nature Customer Service Center GmbH; ProductSafety@springernature.com; ; Europaplatz 3,69115 Heidelberg, Germany; Heidelberg; 69115; Germania