From Contamination to Defects, Faults and Yield Loss: Simulation and Applications: 5 - Rilegato

Libro 27 di 36: Frontiers in Electronic Testing

Maly, Wojciech; Khare, Jitendra B.

 
9780792397144: From Contamination to Defects, Faults and Yield Loss: Simulation and Applications: 5
Rilegato
ISBN 10: 0792397142 ISBN 13: 9780792397144
Casa editrice: Springer-Verlag GmbH, 1996

Sinossi

Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield. Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing. This volume focuses on the core of the interface between manufacturing and testing - the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems. Failure mechanism models are developed and presented which can be used to accurately estimate the probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modelling and design manufacturing.

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Contenuti

Preface. 1: Introduction. 1.1. Trends in IC Manufacturing. 1.2. Yield Loss Mechanisms in ICs. 1.3. Functional Yield Estimation. 1.4. Research Goals. 1.5. Outline. 1.6. References. 2: Background. 2.1. Terminology. 2.2. Point Model. 2.3. Disk Model. 2.4. Experimental Investigation of the Disk Model. 2.5. Summary. 2.6. References. 3: Contamination-Defect-Fault (CDF) Simulation. 3.1. New Contamination Model. 3.2. Contamination-Defect-Fault (CDF) Simulation. 3.3. References. 4: CDF Mapper CODEF. 4.1. CODEF: An Overview. 4.2. Chip Data Base (CDB). 4.3. Process Models. 4.4. Circuit Extraction. 4.5. Netlist Comparison. 4.6. CODEF: Illustration. 4.7. Runtime and Memory Usage. 4.8. References. 5: CODEF Applications. 5.1. Yield Estimation. 5.2. Fault Modeling. 5.3. Failure Analysis. 5.4. References. 6: Possible Extensions. 6.1. CODEF Speed and Memory Considerations. 6.2. Addition of New Process Models. 6.3. Additional Contamination Properties. 6.4. Extraction of Bipolar Transistors. 6.5. Identification of Contamination Parameters. 6.6. References. 7: Conclusions. Appendix A: CMOS Process Flow. Index.

Product Description

Book by Khare Jitendra B Maly Wojciech

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Editore
Springer-Verlag GmbH
Data di pubblicazione
1996
Lingua
Inglese
ISBN 10 
0792397142
ISBN 13 
9780792397144
Rilegatura
Copertina rigida
Numero di pagine
172
Contatto del produttore
ProductSafety@springernature.com
ProductSafety@springernature.com

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Altre edizioni note dello stesso titolo

9781461285953: From Contamination to Defects, Faults and Yield Loss: Simulation and Applications: 5

Edizione in evidenza

ISBN 10:  146128595X ISBN 13:  9781461285953
Casa editrice: Springer, 2011
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