Real-Time Expert Systems Computer Architecture - Rilegato

Hodson, Robert F.; Kandel, Abraham

 
9780849342158: Real-Time Expert Systems Computer Architecture

Sinossi

Real-Time Expert Systems Computer Architecture represents an integration of expert systems and real-time systems by analyzing an innovative computer architecture that combines these two areas of study. Shortcomings of existing systems are analyzed and requirements for a new expert systems computer architecture are presented. The key features of the architecture include such topics as priority processing, temporal reasoning, dataflow architecture, and uncertainty processing. The book thoroughly presents all aspects of system design, implementation, and performance analysis.

Since this book combines technologies, it will serve as an excellent reference for professionals in computer engineering, artificial intelligence, computer architecture, system design, and system engineering.

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Contenuti

REAL TIME EXPERT SYSTEMS. EXPERT SYSTEMS. REAL-TIME SYSTEMS. WHY REAL-TIME EXPERT SYSTEM? EXISTING ARCHITECTURES. von Neumann Architectures. Dataflow Architectures. Multiprocessor Systems. SYSTEM REQUIREMENTS. Timing. Procedural and Declarative Representations. Uncertainty. Environment Interface. Hierarchical Organizational. SUMMARY. SYSTEM DESIGN. TOPOLOGY. PROCESSOR STRUCTURE. Inference Mechanism. Dataflow Methodology. Priority. Uncertainty Processing. External Interface. Temporal Data. Procedural Data. Communication. Dynamic Memories. SUMMARY. SYSTEM IMPLEMENTATION. ARL IMPLEMENTATION. ARL Control. ARL Interfaces. Memory Address Hardware. Rule memory. ARL Memory. Memory Register. Decrement Logic. Link Priority Logic. Negation Logic. Min/Max Logic. ARL Microcode. APQ IMPLEMENTATION. APQ Control. APQ Interfaces. APQ Priority Logic. APQ Memory Organization. APQ Register File. APQ Free Register and Pointer buffer. APQ Empty Queue Logic. APQ Microcode. CPQ IMPLEMENTATION. CPQ Microcode. AP IMPLEMENTATION. AP Control. AP Interfaces. Antecedent Memory. Antecedent Compare Hardware. Wait List Memory. AP Microcode. CP IMPLEMENTATION. CP Code. WM IMPLEMENTATION. MESSAGE BUFFER IMPLEMENTATION. EXTERNAL INTERFACE IMPLEMENTATION. REAL-TIME CLOCK IMPLEMENTATION. SYSTEM RESET IMPLEMENTATION. CLOCK DISTRIBUTION. SUMMARY. SYSTEM SIMULATION. SIMULATION GOALS. SIMULATION APPROACH. Discrete-Event Simulation. Process Concept. Resource Concept. Process-Resource Example. Program Structure. Simulation Model. SIMULATION RESULTS. Peak and Typical Processing Rates. Effect of ICUs. Effect of Tasks. Effect of Pruning. CONCLUSION. BIBLIOGRAPHY. HARDWARE DIAGRAMS. ARL HARDWARE. APQ HARDWARE. CPQ HARDWARE. AP HARDWARE. CP HARDWARE. WM HARDWARE. MB HARDWARE. EXTERNAL INTERFACE HARDWARE. REAL-TIME CLOCK HARDWARE. SYSTEM RESET HARDWARE. CLOCK GENERATION HARDWARE.

Product Description

Book by Hodson Robert F Kandel Abraham

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