Articoli correlati a Yield Simulation for Integrated Circuits: 33
Sinossi
In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself.
Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.
Contenuti
1. Introduction.- 2. Background.- 3. Defect Models.- 4. Defect Statistics.- 5. Fault Analysis.- 6. VLASIC Implementation.- 7. Redundancy Analysis System.- 8. Fabrication Data.- 9. Conclusions and Current Research.- References.
Le informazioni nella sezione "Su questo libro" possono far riferimento a edizioni diverse di questo titolo.
- EditoreSpringer
- Data di pubblicazione2010
- ISBN 10 1441952012
- ISBN 13 9781441952011
- RilegaturaCopertina flessibile
- LinguaInglese
- Numero di pagine224
Compra nuovo
Visualizza questo articolo
EUR 163,06
EUR 3,55 per la spedizione in U.S.A.
Destinazione, tempi e costiAltre edizioni note dello stesso titolo
Risultati della ricerca per Yield Simulation for Integrated Circuits: 33
Foto dell'editore
Yield Simulation for Integrated Circuits (The Springer International Series in Engineering and Computer Science)
Da: Lucky's Textbooks, Dallas, TX, U.S.A.
Valutazione del venditore 5 su 5 stelle
Condizione: New. Codice articolo ABLIING23Mar2411530296580
Quantità: Più di 20 disponibili
Foto dell'editore
Yield Simulation for Integrated Circuits (The Springer International Series in Engineering and Computer Science)
Da: Ria Christie Collections, Uxbridge, Regno Unito
Valutazione del venditore 5 su 5 stelle
Condizione: New. In. Codice articolo ria9781441952011_new
Quantità: Più di 20 disponibili
Immagini fornite dal venditore
Yield Simulation for Integrated Circuits
Da: AHA-BUCH GmbH, Einbeck, Germania
Valutazione del venditore 5 su 5 stelle
Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself. Codice articolo 9781441952011
Quantità: 1 disponibili
Immagini fornite dal venditore
Yield Simulation for Integrated Circuits
Print on DemandDa: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
Valutazione del venditore 5 su 5 stelle
Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself. 224 pp. Englisch. Codice articolo 9781441952011
Quantità: 2 disponibili
Foto dell'editore
Yield Simulation for Integrated Circuits
Da: Revaluation Books, Exeter, Regno Unito
Valutazione del venditore 5 su 5 stelle
Paperback. Condizione: Brand New. 228 pages. 9.00x6.00x0.51 inches. In Stock. Codice articolo x-1441952012
Quantità: 2 disponibili
Foto dell'editore
Yield Simulation for Integrated Circuits (The Springer International Series in Engineering and Computer Science (33))
Da: Mispah books, Redhill, SURRE, Regno Unito
Valutazione del venditore 4 su 5 stelle
Paperback. Condizione: Like New. Like New. book. Codice articolo ERICA77314419520126
Quantità: 1 disponibili