Articoli correlati a Low Power Networks-on-Chip
Sinossi
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.
Dalla quarta di copertina
Low Power Networks-on-Chip Edited by: (editors)Cristina Silvano Marcello LajoloGianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issuesstill represent one of the limiting factors in integrating multi- and many-coreson a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.
Le informazioni nella sezione "Su questo libro" possono far riferimento a edizioni diverse di questo titolo.
Compra nuovo
Visualizza questo articolo
EUR 128,41
EUR 9,70 per la spedizione da Germania a Italia
Destinazione, tempi e costiAltre edizioni note dello stesso titolo
Risultati della ricerca per Low Power Networks-on-Chip
Foto dell'editore
Low Power Networks-On-Chip
Da: Buchpark, Trebbin, Germania
Valutazione del venditore 5 su 5 stelle
Condizione: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher. Codice articolo 7749499/12
Quantità: 2 disponibili
Foto dell'editore
Low Power Networks-On-Chip
Da: Buchpark, Trebbin, Germania
Valutazione del venditore 5 su 5 stelle
Condizione: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher. Codice articolo 7749499/2
Quantità: 2 disponibili
Foto dell'editore
Low Power Networks-on-Chip
Da: Patrico Books, Apollo Beach, FL, U.S.A.
Valutazione del venditore 5 su 5 stelle
hardcover. Condizione: As New. Ships Out Tomorrow! Codice articolo 230418104
Quantità: 1 disponibili
Immagini fornite dal venditore
Low Power Networks-on-Chip
Print on DemandDa: moluna, Greven, Germania
Valutazione del venditore 5 su 5 stelle
Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architecturesApplies state-of-the-art, low-power design techniques to the design of . Codice articolo 4176185
Quantità: Più di 20 disponibili
Foto dell'editore
Low Power Networks-on-Chip (eng)
Print on DemandDa: Brook Bookstore On Demand, Napoli, NA, Italia
Valutazione del venditore 5 su 5 stelle
Condizione: new. Questo è un articolo print on demand. Codice articolo e514e12d7cc30150473815f45ab4b5cc
Quantità: Più di 20 disponibili
Foto dell'editore
Low Power Networks-on-Chip
Da: Ria Christie Collections, Uxbridge, Regno Unito
Valutazione del venditore 5 su 5 stelle
Condizione: New. In. Codice articolo ria9781441969101_new
Quantità: Più di 20 disponibili
Immagini fornite dal venditore
Low Power Networks-On-Chip
Print on DemandDa: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
Valutazione del venditore 5 su 5 stelle
Buch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issuesstill represent one of the limiting factors in integrating multi- and many-coreson a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings. 287 pp. Englisch. Codice articolo 9781441969101
Quantità: 2 disponibili
Immagini fornite dal venditore
Low Power Networks-On-Chip
Da: AHA-BUCH GmbH, Einbeck, Germania
Valutazione del venditore 5 su 5 stelle
Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issuesstill represent one of the limiting factors in integrating multi- and many-coreson a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings. Codice articolo 9781441969101
Quantità: 2 disponibili
Foto dell'editore
Low Power Networks-On-Chip
Da: Books Puddle, New York, NY, U.S.A.
Valutazione del venditore 4 su 5 stelle
Condizione: New. pp. 308. Codice articolo 262168999
Quantità: 4 disponibili
Foto dell'editore
Low Power Networks-on-Chip
Da: Lucky's Textbooks, Dallas, TX, U.S.A.
Valutazione del venditore 5 su 5 stelle
Condizione: New. Codice articolo ABLIING23Mar2411530297193
Quantità: Più di 20 disponibili