Articoli correlati a Comparative analysis of Sequential and Concurrent processing...
- EditoreLAP LAMBERT Academic Publishing
- Data di pubblicazione2017
- ISBN 10 3330085371
- ISBN 13 9783330085374
- RilegaturaCopertina flessibile
- Numero di pagine72
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Comparative analysis of Sequential and Concurrent processing for float
Editore:
LAP Lambert Academic Publishing Jun 2017
(2017)
ISBN 10: 3330085371
ISBN 13: 9783330085374
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Descrizione libro Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Floating point adders are hard to implement on reconfigurable devices because of complexity of their algorithm. Proposed work describes the implementation of floating point adder using sequential and concurrent processing on reconfigurable hardware. Implementation of floating point adder using sequential processing utilizes less chip area but with significant increase in combinational delay and clock period as compared with concurrent processing. Implementation of floating point adder using concurrent processing on Virtex 4 consumes 7% chip area with a combinational delay of 24.201nsec without offset and 27.891nsec offset delay and implementation of floating point adder on Spartan 2E using concurrent processing utilizes 401 slices with a combinational delay of 56.679nsec and consumes 188908 Kbytes of memory while implementing same on Spartan 2E using sequential processing consumes 52% chip area with a combinational delay of 69.987nsec and it implies that clock speed of concurrent processing is more than sequential processing but area consumption is also more. 72 pp. Englisch. Codice articolo 9783330085374
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Comparative analysis of Sequential and Concurrent processing for float
Editore:
LAP Lambert Academic Publishing
(2017)
ISBN 10: 3330085371
ISBN 13: 9783330085374
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Taschenbuch
Quantità: 1
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Descrizione libro Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Floating point adders are hard to implement on reconfigurable devices because of complexity of their algorithm. Proposed work describes the implementation of floating point adder using sequential and concurrent processing on reconfigurable hardware. Implementation of floating point adder using sequential processing utilizes less chip area but with significant increase in combinational delay and clock period as compared with concurrent processing. Implementation of floating point adder using concurrent processing on Virtex 4 consumes 7% chip area with a combinational delay of 24.201nsec without offset and 27.891nsec offset delay and implementation of floating point adder on Spartan 2E using concurrent processing utilizes 401 slices with a combinational delay of 56.679nsec and consumes 188908 Kbytes of memory while implementing same on Spartan 2E using sequential processing consumes 52% chip area with a combinational delay of 69.987nsec and it implies that clock speed of concurrent processing is more than sequential processing but area consumption is also more. Codice articolo 9783330085374
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Comparative analysis of Sequential and Concurrent processing for float
Editore:
LAP LAMBERT Academic Publishing
(2017)
ISBN 10: 3330085371
ISBN 13: 9783330085374
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Descrizione libro Paperback. Condizione: Brand New. 72 pages. 8.66x5.91x0.17 inches. In Stock. Codice articolo 3330085371
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Comparative analysis of Sequential and Concurrent processing for float
Editore:
LAP LAMBERT Academic Publishing
(2017)
ISBN 10: 3330085371
ISBN 13: 9783330085374
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Descrizione libro Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Gumber KaranKaran Gumber received the M.E. degree in electronics & comm. engineering from the UIET, Panjab University under the supervision of Sharmelee Thangjam. He is currently pursuing his Ph.D from IIT Roorkee under the supervisi. Codice articolo 151237222
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