Compressor on Multiplier Application: Design and implementation of 4 to 2 compressor for multiplier applications

DWIBEDI, RAJAT KUMAR; L.K, HEMA; L, PATTATHU RANI

ISBN 10: 6204752766 / ISBN 13: 9786204752761

Editore: LAP LAMBERT Academic Publishing, 2022

Riguardo questo articolo

Codice articolo 26397320678

Dati bibliografici

• Titolo: Compressor on Multiplier Application: Design and implementation of 4 to 2 compressor for multiplier applications
• Editore: LAP LAMBERT Academic Publishing
• Data di pubblicazione: 2022
• Lingua: Inglese
• ISBN 10: 6204752766
• ISBN 13: 9786204752761
• Rilegatura: Brossura
• Condizione: New

Descrizione articolo

Riassunto

Multipliers are perhaps the main structure components in PC math, and they're commonly seen in digital signal processors. High-speed multipliers are in high demand in a variety of computing applications and some examples include computer graphics, scientific calculations, picture processing etcetera. The multiplier speed decides how rapidly the processors run, and designers are right now chipping away at fast with low power utilization. The three distinct stages in the multiplier design comprises of a partial product generator, a partial product reduction, and addition stage. Main stage which improves the overall multiplier performance is the reduction stage if there is a considerable change in this stage the overall multiplication delay, power, and area reduces drastically. Compressors are typically used to accumulate partial products since these add to the decrease just as the diminishing of the basic way, which is critical to keep up the circuit's exhibition.