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Low-Noise Low-Power Design for Phase-Locked Loops

Feng Zhao

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ISBN 10: 3319121995 / ISBN 13: 9783319121994
Editore: Springer-Verlag Gmbh Jan 2015, 2015
Nuovi Condizione: Neu Buch
Da Rhein-Team Lörrach Ivano Narducci e.K. (Lörrach, Germania)

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Neuware - This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters. 96 pp. Englisch. Codice inventario libreria 9783319121994

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Titolo: Low-Noise Low-Power Design for Phase-Locked ...

Casa editrice: Springer-Verlag Gmbh Jan 2015

Data di pubblicazione: 2015

Legatura: Buch

Condizione libro:Neu

Descrizione articolo

Riassunto:

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation.  The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage.  Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.  

Sinossi:

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the most popular PLL design techniques and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. This technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.

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