Processor Architecture

Jurij Silc

ISBN 10: 3540647988 / ISBN 13: 9783540647980

Editore: Springer Berlin Heidelberg, Springer Berlin Heidelberg Jun 1999, 1999

Riguardo questo articolo

Neuware -Today's microprocessors are the powerful descendants of the von Neumann 1 computer dating back to a memo of Burks, Goldstine, and von Neumann of 1946. The so-called von Neumann architecture is characterized by a se quential control flow resulting in a sequential instruction stream. A program counter addresses the next instruction if the preceding instruction is not a control instruction such as, e. g. , jump, branch, subprogram call or return. An instruction is coded in an instruction format of fixed or variable length, where the opcode is followed by one or more operands that can be data, addresses of data, or the address of an instruction in the case of a control instruction. The opcode defines the types of operands. Code and data are stored in a common storage that is linear, addressed in units of memory words (bytes, words, etc. ). The overwhelming design criterion of the von Neumann computer was the minimization of hardware and especially of storage. The most simple implementation of a von Neumann computer is characterized by a microar chitecture that defines a closely coupled control and arithmetic logic unit (ALU), a storage unit, and an I/O unit, all connected by a single connection unit. The instruction fetch by the control unit alternates with operand fetches and result stores for the AL U.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 416 pp. Englisch.

Codice articolo 9783540647980

Dati bibliografici

• Titolo: Processor Architecture
• Editore: Springer Berlin Heidelberg, Springer Berlin Heidelberg Jun 1999
• Data di pubblicazione: 1999
• Lingua: Inglese
• ISBN 10: 3540647988
• ISBN 13: 9783540647980
• Rilegatura: Taschenbuch
• Condizione: Neu
• Dimensioni: 235 L x 155 A x 23 P (millimetri) 235 millimetri di larghezza per 155 millimetri di altezza per 23 millimetri di profondità
• Peso: 628 grammi

Descrizione articolo

Riassunto

A survey of architectural mechanisms and implementation techniques for exploiting fine- and coarse-grained parallelism within microprocessors. Beginning with a review of past techniques, the monograph provides a comprehensive account of state-of-the-art techniques used in microprocessors, covering both the concepts involved and implementations in sample processors. The whole is rounded off with a thorough review of the research techniques that will lead to future microprocessors. XXXXXXX Neuer Text This monograph surveys architectural mechanisms and implementation techniques for exploiting fine-grained and coarse-grained parallelism within microprocessors. It presents a comprehensive account of state-of-the-art techniques used in microprocessors that covers both the concepts involved and possible implementations. The authors also provide application-oriented methods and a thorough review of the research techniques that will lead to the development of future processors.

Dalla quarta di copertina

This monograph surveys architectural mechanisms and implementation techniques for exploiting fine-grained and coarse-grained parallelism within microprocessors. It starts with a review of past techniques, continues with a comprehensive account of state-of-the-art techniques used in microprocessors that covers both the concepts involved and implementations in sample processors, and ends with a thorough review of the research techniques that will lead to future microprocessors.