Design reuse is not just a topic of research but a real industrial necessity in the microelectronic domain and thus driving the competitiveness of relevant areas like for example telecommunication or automotive. Most companies have already dedicated a department or a central unit that transfer design reuse into reality. All main EDA conferences include a track to the topic, and even specific conferences have been established in this area, both in the USA and in Europe.
Virtual Components Design and Reuse presents a selection of articles giving a mature and consolidated perspective to design reuse from different points of view. The authors stem from all relevant areas: research and academia, IP providers, EDA vendors and industry.
Some classical topics in design reuse, like specification and generation of components, IP retrieval and cataloguing or interface customisation, are revisited and discussed in depth. Moreover, new hot topics are presented, among them IP quality, platform-based reuse, software IP, IP security, business models for design reuse, and major initiatives like the MEDEA EDA Roadmap.

Contenuti

List of figures. List of tables. 1. Virtual components - from research to business; J. Haase. 2. Evaluation of technology and the medea design automation roadmap; J. Borel, et al. 3. Productivity in VC reuse: linking SOC platforms to abstract systems design methodology; G. Martin. 4. Software IP in embedded systems; C. B�ke, et al. 5. ARDID: a tool and a model for the quality analysis of VHDL based designs; Y. Torroja, et al. 6. A VHDL analysis environment for design reuse; C. Costi, D.M. Miller. 7. Lambda-block analysis of VHDL for design reuse; W. Fornaciari, et al. 8. IP retrieval by solving constraint satisfaction problems; M. Koegst, et al. 9. Cryptographic reuse library; A. Schubert, et al. 10.A VHDL reuse component model for mixed abstraction level simulation and behavioral synthesis; C. Hansen, et al. 11. Virtual component interfaces; M.M. Kamal Hashmi. 12. A method for interface customization of soft IP cores; R. Siegmund, D. M�ller. 13. Modeling assistant - a flexible VCM generator in VHDL; A. Puika. 14. Reusing IPS to implement a SPARC� SOC; S. Olcoz, et al. 15. Hardwwwired: using the web as repository of VHDL components; A. Sarmento, et al. References. Index. Glossary.

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