Editore: North-Holland, 1986
Lingua: Inglese
Da: Antiquariat Bookfarm, Löbnitz, Germania
EUR 7,50
Convertire valutaQuantità: 1 disponibili
Aggiungi al carrelloHardcover. Ehem. Bibliotheksexemplar mit Signatur und Stempel. GUTER Zustand, ein paar Gebrauchsspuren. Ex-library with stamp and library-signature. GOOD condition, some traces of use. X-15807 Sprache: Englisch Gewicht in Gramm: 550.
Da: liu xing, Nanjing, JS, Cina
EUR 76,50
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Aggiungi al carrellopaperback. Condizione: New. Language:Chinese.Paperback. Pub Date: 2024-07 Pages: 208 Publisher: Publishing House of Electronic Industry This book is written in accordance with the recent new vocational education and teaching reform requirements. based on the actual needs of the integrated circuit industry for layout design job skills. with integrated circuit layout design as the main line of work. combined with the author's many years of corporate practice experience and teaching experience. as well as the results of th.
Editore: Sole distributors for the U.S.A. and Canada, Elsevier Science Pub. Co, 1986
ISBN 10: 0444878947 ISBN 13: 9780444878946
Lingua: Inglese
Da: Goodwill of Silicon Valley, SAN JOSE, CA, U.S.A.
EUR 17,59
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Aggiungi al carrelloCondizione: very_good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in very good condition! The cover and any other included accessories are also in very good condition showing some minor use. The spine is straight, there are no rips tears or creases on the cover or the pages.
Editore: Sole distributors for the U.S.A. and Canada, Elsevier Science Pub. Co, 1986
ISBN 10: 0444878947 ISBN 13: 9780444878946
Lingua: Inglese
Da: Goodwill of Silicon Valley, SAN JOSE, CA, U.S.A.
EUR 17,59
Convertire valutaQuantità: 1 disponibili
Aggiungi al carrelloCondizione: good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Good condition! Any other included accessories are also in Good condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear.
ISBN 10: 7121298074 ISBN 13: 9787121298073
Da: liu xing, Nanjing, JS, Cina
EUR 69,53
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Aggiungi al carrellopaperback. Condizione: New. Paperback. Pub Date:2016-08-01 Pages:272 Language: Publisher: Chinese Electronic Industry Press book based on the Cadence Virtuoso layout design tools and Mentor Calibre layout verification tool. take a gradual approach. introduced by Cadence and Virtuoso.
ISBN 10: 7115507678 ISBN 13: 9787115507679
Da: liu xing, Nanjing, JS, Cina
EUR 73,27
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Aggiungi al carrellopaperback. Condizione: New. Paperback. Pub Date: 2019-04-01 Pages: 158 Language: Chinese Publisher: People's Posts and Telecommunications Press This book introduces the design theory and practical methods of digital integrated circuits. through a complete CPU circuit RTL level verification. synthesis and layout Designed to give readers a systematic and comprehensive understanding of the ASIC design process. The main contents of this book include.
ISBN 10: 7302640904 ISBN 13: 9787302640905
Da: liu xing, Nanjing, JS, Cina
EUR 113,61
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Aggiungi al carrellopaperback. Condizione: New. Language:Chinese.Paperback. Pub Date: 2023-11 Pages: 404 Publisher: Tsinghua University Press This book focuses on the overall explanation of integrated circuit EDA usage technology and design technology. This book comprehensively introduces the use of international mainstream EDA tools. and systematically explains the EDA tool processes and design techniques of analog integrated circuits and digital integrated circuits. This book introduces the basics of SPICE simulation. including integrate.
ISBN 10: 7111737806 ISBN 13: 9787111737803
Da: liu xing, Nanjing, JS, Cina
EUR 157,18
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Aggiungi al carrellopaperback. Condizione: New. Language:Chinese.Paperback. Pub Date: 2023-12 Pages: 483 Publisher: Machinery Industry Press This book focuses on the field of CMOS analog integrated circuit layout design. Starting from the basic concepts of layout. design methods and EDA tools. it gradually introduces CMOS analog integrated circuit layout planning. . layout. design to tape-out; it introduces in detail the current mainstream analog integrated circuit layout design and verification tools - Cadence IC 6.1.7 and Siemens EDA Cal.