Timing Verification of Application-Specific Integrated Circuits - Rilegato

Nekoogar, Farzad

Rilegato

ISBN 10: 0137943482 ISBN 13: 9780137943487

Casa editrice: Prentice Hall, 1999

Riassunto

Reviewers tell us that Case/Fair is one of the all-time bestselling principles of economics texts because they trust it to be clear, thorough and complete.  This well-respected author team is joined for the 9^th edition by a new co-author, Sharon Oster.  Sharon’s research and teaching experience brings new coverage of modern topics and an applied approach to economic theory, as demonstrated in the new Economics in Practice feature.
Introduction to Economics; Concepts and Problems in Macroeconomics; The Core of Macroeconomic Theory; Further Macroeconomic Issues; The World Economy
For those looking for a trusted and authoritative principles of macroeconomics text that focuses on international econmies as well as the Keynesian Cross. Case/Fair/Oster believe strongly, that a text should use the Keynesian Cross carefully and systematically, to build up to the AD/AS model.  One of the great benefits of this approach, is that students of economics won’t mistakenly apply what they learned about simple demand and supply to aggregate demand & supply.  (A detailed summary of this approach can be found in the preface).

Su questo libro

Informazioni sull?autore

FARZAD NEKOOGAR, formerly a Technical Manager at Intrinsix Corp., has extensive practical experience verifying timing of ASICs, FPGAs, and systems-on-a-chip. He is a lecturer at the University of California at Davis, and is the author ofDigital Control Using Digital Signal Processing, published by Prentice Hall PTR.

Dalla quarta di copertina

79434-7

It's About Time

In today's high-speed designs, timing analysis is critical to success. This is the first book to focus exclusively on these crucial timing issues, with special emphasis on timing verification of ASICs. Timing Verification of Application Specific Integrated Circuits (ASICs) highlights principles and techniques over specific tools. This method makes the materials applicable to a variety of logic design approaches, especially in the field of deep submicron digital design. Topics include:

• Clock definitions, multicycle paths, false paths, and phase-locked loops
• Behavioral and structural RTL coding for timing
• Timing analysis of FPGAs
• Pre and Post layout timing analysis
• Synthesis and Timing constraints
• EDA timing tools

Numerous design examples and Verilog codes offer practical illustrations of all the concepts. Timing Verification of Application Specific Integrated Circuits (ASICs) is a must for all logic designers concerned with the accuracy of timing and clock issues.

Dettagli dell'edizione

• Editore: Prentice Hall
• Data di pubblicazione: 1999
• Lingua: Inglese
• ISBN 10: 0137943482
• ISBN 13: 9780137943487
• Rilegatura: Copertina rigida
• Numero edizione: 1
• Numero di pagine: 179
• Contatto del produttore: non disponibile
• Persona responsabile: Yeepin GmbH; 492000000000; sunshine12232@outlook.com; ; Alleestr.11; Kaiserslautern; Rheinland-Pfalz; 67655; Germania