This edition presents the new IEEE 1364-2001 standard of The Verilog Hardware Description Language. It offers updated examples that illustrated the new features of the language as well as a cross- referenced guide to the new and old features.
Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.
Thomas & Moorby's The Verilog® Hardware Description Language has become the standard reference text for Verilog.
The Verilog® Hardware Description Language, Fifth Edition, is a valuable resource for engineers and students interested in describing, simulating, and synthesizing digital systems; the extensive number of simulatable examples and wide range of representation styles covered ensure its quick use in design.
The book is also ready for use in university courses, having been used for introductory logic design and simulation through advanced VLSI design courses. An appendix with tutorial help and a work-along style is keyed into the introduction for new students. Material supporting a computer-aided design course on the inner working of simulators is also included.
Le informazioni nella sezione "Su questo libro" possono far riferimento a edizioni diverse di questo titolo.
GRATIS per la spedizione in U.S.A.
Destinazione, tempi e costiEUR 3,45 per la spedizione in U.S.A.
Destinazione, tempi e costiDa: BooksRun, Philadelphia, PA, U.S.A.
Paperback. Condizione: Very Good. 5th ed. 2002. It's a well-cared-for item that has seen limited use. The item may show minor signs of wear. All the text is legible, with all pages included. It may have slight markings and/or highlighting. Codice articolo 0387849300-8-1
Quantità: 1 disponibili
Da: HPB-Red, Dallas, TX, U.S.A.
paperback. Condizione: Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority! Codice articolo S_374320388
Quantità: 1 disponibili
Da: St Vincent de Paul of Lane County, Eugene, OR, U.S.A.
Condizione: Good. COVER SHOWS SOME GENERAL WEAR, SUCH AS SCRATCHES, RUBBING, STAINING, STICKER AND/OR GLUE RESIDUE AND CREASES. CLEAR COATING ON COVER IS COMING UP ON FRONT COVER.BOOK HAS PREVIOUS OWNERS NAME IN IT. paperback 100% of proceeds go to charity! Good condition with all pages in tact. Item shows signs of use and may have cosmetic defects. Codice articolo U-06-4601
Quantità: 1 disponibili
Da: Goodwill of Silicon Valley, SAN JOSE, CA, U.S.A.
Condizione: good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Good condition! Any other included accessories are also in Good condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear. Codice articolo GWSVV.0387849300.G
Quantità: 1 disponibili
Da: Lucky's Textbooks, Dallas, TX, U.S.A.
Condizione: New. Codice articolo ABLIING23Feb2215580173411
Quantità: Più di 20 disponibili
Da: GreatBookPrices, Columbia, MD, U.S.A.
Condizione: New. Codice articolo 5833018-n
Quantità: Più di 20 disponibili
Da: Ria Christie Collections, Uxbridge, Regno Unito
Condizione: New. In. Codice articolo ria9780387849300_new
Quantità: Più di 20 disponibili
Da: Chiron Media, Wallingford, Regno Unito
PF. Condizione: New. Codice articolo 6666-IUK-9780387849300
Quantità: 10 disponibili
Da: GreatBookPricesUK, Woodford Green, Regno Unito
Condizione: New. Codice articolo 5833018-n
Quantità: Più di 20 disponibili
Da: Grand Eagle Retail, Bensenville, IL, U.S.A.
Paperback. Condizione: new. Paperback. XV From the Old to the New xvii Acknowledgments xx| Verilog A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits 11 Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Procedural Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment (" This edition presents the new IEEE 1364-2001 standard of The Verilog Hardware Description Language. It offers updated examples that illustrated the new features of the language as well as a cross- referenced guide to the new and old features. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Codice articolo 9780387849300
Quantità: 1 disponibili