Digital Systems Design With Vhdl and Synthesis: An Integrated Approach - Rilegato

Chang, K. C.

Rilegato

ISBN 10: 0769500234 ISBN 13: 9780769500232

Casa editrice: IEEE Computer Society, 1999

Riassunto

K.C. Chang presents an integrated approach to digital design principles, processes, and implementations to help the reader design increasingly complex systems within shorter design cycles. Chang introduces digital design concepts, VHDL coding, VHDL simulation, synthesis commands, and strategies together.

Digital Systems Design with VHDL and Synthesis focuses on the ultimate product of the design cycle: the implementation of a digital design. Many of the design techniques and considerations illustrated in the text are examples of actual real-world designs.

Unique features of the book include the following:

• VHDL code explained line by line to capture the logic behind the design concepts
• Simulation waveforms, synthesized schematics, and results are shown, verified, and analyzed
• VHDL code is synthesized and commands and strategies are discussed
• Variations on the design techniques and common mistakes are addressed
• Demonstrated standard cell, gate array, and FPGA three design processes, each with a complete design case study
• Test bench, post-layout verification, and test vector generation processes are illustrated

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Informazioni sull?autore

Kwang-chih Chang, commonly known as K.C. Chang, was a Chinese-American archaeologist and sinologist. He was the John E. Hudson Professor of archaeology at Harvard University, Vice-President of the Academia Sinica, and a curator at the Peabody Museum of Archaeology and Ethnology.

Digital Systems Design with VHDL and Synthesis focuses on the ultimate product of the design cycle: the implementation of a digital design. Many of the design techniques and considerations illustrated in the text are examples of actual real-world designs.

Unique features of the book include the following:

• VHDL code explained line by line to capture the logic behind the design concepts
• Simulation waveforms, synthesized schematics, and results are shown, verified, and analyzed
• VHDL code is synthesized and commands and strategies are discussed
• Variations on the design techniques and common mistakes are addressed
• Demonstrated standard cell, gate array, and FPGA three design processes, each with a complete design case study
• Test bench, post-layout verification, and test vector generation processes are illustrated

Dettagli dell'edizione

• Editore: IEEE Computer Society
• Data di pubblicazione: 1999
• Lingua: Inglese
• ISBN 10: 0769500234
• ISBN 13: 9780769500232
• Rilegatura: Copertina rigida
• Numero di pagine: 499
• Contatto del produttore: non disponibile
• Persona responsabile: non disponibile