The first edition of this text offered a common sense method for simplifying and unifying assertion specification by creating a set of pre-defined specification modules that could be instantiated within the designer's RTL. Since the release of the first edition, an entire industry-wide initiative for assertion specification has emerged based on ideas presented in the first edition. This initiative is known as the Open Verification Library Initiative. This standard enables the design engineer to "specify once", then target the same RTL assertion specification over multiple verification processes, such as traditional simulation, semi-formal and formal verification tools. The Open Verification Library Initiative is an empowering technology that should benefit design and verification engineers while providing unity to the EDA community. The second edition of "Principles of Verifiable RTL Design" expands the discussion of assertion specification.
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Foreword. Preface. 1. Introduction. 2. The Verification Process. 3. Coverage, Events and Assertions. 4. RTL Methodology Basics. 5. RTL Logic Simulation. 6. RTL Formal Verification. 7. Verifiable RTL Style. 8. The Bad Stuff. 9. Verifiable RTL Tutorial. 10. Principles of Verifiable RTL Design. Bibliography. A. Comparing Verilog Construct Performance. B. Quick Reference. C. Assertion Monitors.
Book by Bening Lionel Foster Harry D
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