Digital Systems Design and Prototyping: Using Field Programmable Logic and Hardware Description Languages - Rilegato

Salcic, Zoran; Smailagic, Asim

Rilegato

ISBN 10: 0792379209 ISBN 13: 9780792379201

Casa editrice: Kluwer Academic Pub, 2000

Riassunto

Digital Systems Design and Prototyping: Using Field Programmable Logic and Hardware Description Languages, Second Edition covers the subject of digital systems design using two important technologies: Field Programmable Logic Devices (FPLDs) and Hardware Description Languages (HDLs). These two technologies are combined to aid in the design, prototyping, and implementation of a whole range of digital systems from very simple ones replacing traditional glue logic to very complex ones customized as the applications require.
Three HDLs are presented: VHDL and Verilog, the widely used standard languages, and the proprietary Altera HDL (AHDL). The chapters on these languages serve as tutorials and comparisons are made that show the strengths and weaknesses of each language.
A large number of examples are used in the description of each language providing insight for the design and implementation of FPLDs.
With the addition of the Altera UP-1 prototyping board, all examples can be tested and verified in a real FPLD.
Digital Systems Design and Prototyping: Using Field Programmable Logic and Hardware Description Languages, Second Edition is designed as an advanced level textbook as well as a reference for the professional engineer.

Su questo libro

Contenuti

Preface to the Second Edition. 1. Introduction to Field Programmable Logic Devices. 2. Examples of Major FPLD Families. 3. Design Tools and Logic Design with FPLDS. 4. Introduction to Design Using AHDL. 5. Advanced AHDL. 6. Design Examples. 7. SIMP - A Simple Customizable Microprocessor. 8. Rapid Prototyping Using FPLDS - Vuman Case Study. 9. Introduction to VHDL. 10. Objects, Data Types and Processes. 11. VHDL and Logic Synthesis. 12. Example Designs and Problems. 13. Introduction to Verilog HDL. 14. Verilog and Logic Synthesis by Examples. 15. A Verilog Example: Pipelined SimP. Glossary. Selected Reading. Web Resources. Index.

Product Description

Book by Salcic Zoran Smailagic Asim

Dettagli dell?edizione

• Editore: Kluwer Academic Pub
• Data di pubblicazione: 2000
• Lingua: Inglese
• ISBN 10: 0792379209
• ISBN 13: 9780792379201
• Rilegatura: Copertina rigida
• Numero di pagine: 620
• Contatto del produttore: non disponibile
• Persona responsabile: CMN Printpool Inh. Mathis Neumann; https://www.also.com/ec/cms5/en_6000/6000/index.jsp; ; Friedrich-Karl-Str. 9; Hamburg; Germania