Formal Equivalence Checking and Design Debugging: 12 - Rilegato
Libro 29 di 36: Frontiers in Electronic Testing
Sinossi
Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'
Kurt Keutzer, University of California, Berkeley
Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.
Contenuti
Foreword. Preface. 1. Introduction. Part I: Equivalence Checking. 2. Symbolic Verification. 3. Incremental Verification for Combinational Circuits. 4. Incremental Verification for Sequential Circuits. 5. AQUILA: A Local BDD-Based Equivalence Verifier. 6. Algorithm for Verifying Retimed Circuits. 7. RTL-to-Gate Verification. Part II: Logic Debugging. 8. Introduction to Logic Debugging. 9. ErrorTracer: Error Diagnosis by Fault Simulation. 10. Extension to Sequential Error Diagnosis. 11. Incremental Logic Rectification. Bibliography. Index.
Product Description
Book by ShiYu Huang KwangTing Tim Cheng
Le informazioni nella sezione "Su questo libro" possono far riferimento a edizioni diverse di questo titolo.
Altre edizioni note dello stesso titolo
Risultati della ricerca per Formal Equivalence Checking and Design Debugging: 12
Immagini fornite dal venditore
Formal Equivalence Checking and Design Debugging
Print on DemandDa: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
Valutazione del venditore 5 su 5 stelle
Buch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley 252 pp. Englisch. Codice articolo 9780792381846
Compra nuovo
EUR 160,49
Spedizione EUR 23,00
Spedito da Germania a U.S.A.
Spedito da Germania a U.S.A.
Quantità: 2 disponibili
Immagini fornite dal venditore
Formal Equivalence Checking and Design Debugging
Print on DemandDa: moluna, Greven, Germania
Valutazione del venditore 5 su 5 stelle
Gebunden. Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and . Codice articolo 5970738
Compra nuovo
EUR 162,51
Spedizione EUR 48,99
Spedito da Germania a U.S.A.
Spedito da Germania a U.S.A.
Quantità: Più di 20 disponibili
Foto dell'editore
Formal Equivalence Checking and Design Debugging (Frontiers in Electronic Testing, 12)
Da: Ria Christie Collections, Uxbridge, Regno Unito
Valutazione del venditore 5 su 5 stelle
Condizione: New. In. Codice articolo ria9780792381846_new
Compra nuovo
EUR 198,71
Spedizione EUR 13,82
Spedito da Regno Unito a U.S.A.
Spedito da Regno Unito a U.S.A.
Quantità: Più di 20 disponibili
Immagini fornite dal venditore
Formal Equivalence Checking and Design Debugging
Print on DemandDa: preigu, Osnabrück, Germania
Valutazione del venditore 5 su 5 stelle
Buch. Condizione: Neu. Formal Equivalence Checking and Design Debugging | Shi-Yu Huang (u. a.) | Buch | Frontiers in Electronic Testing | xviii | Englisch | 1998 | Springer | EAN 9780792381846 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand. Codice articolo 102563064
Compra nuovo
EUR 168,50
Spedizione EUR 70,00
Spedito da Germania a U.S.A.
Spedito da Germania a U.S.A.
Quantità: 5 disponibili
Foto dell'editore
Formal Equivalence Checking and Design Debugging
Da: Buchpark, Trebbin, Germania
Valutazione del venditore 5 su 5 stelle
Condizione: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley. Codice articolo 1361249/202
Compra usato
EUR 136,55
Spedizione EUR 105,00
Spedito da Germania a U.S.A.
Spedito da Germania a U.S.A.
Quantità: 2 disponibili
Immagini fornite dal venditore
Formal Equivalence Checking and Design Debugging
Editore:
Springer, Springer Jun 1998, 1998
ISBN 10: 079238184X
ISBN 13: 9780792381846
Nuovo
Rilegato
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germania
Valutazione del venditore 5 su 5 stelle
Buch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.From the Foreword:`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'Kurt Keutzer, University of California, BerkeleySpringer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 252 pp. Englisch. Codice articolo 9780792381846
Compra nuovo
EUR 192,59
Spedizione EUR 60,00
Spedito da Germania a U.S.A.
Spedito da Germania a U.S.A.
Quantità: 1 disponibili
Foto dell'editore
Formal Equivalence Checking and Design Debugging
Da: Books Puddle, New York, NY, U.S.A.
Valutazione del venditore 4 su 5 stelle
Condizione: New. pp. 252 Indices. Codice articolo 263104345
Compra nuovo
EUR 249,81
Spedizione EUR 3,40
Spedito in U.S.A.
Spedito in U.S.A.
Quantità: 4 disponibili
Immagini fornite dal venditore
Formal Equivalence Checking and Design Debugging
Da: AHA-BUCH GmbH, Einbeck, Germania
Valutazione del venditore 5 su 5 stelle
Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley. Codice articolo 9780792381846
Compra nuovo
EUR 201,36
Spedizione EUR 62,74
Spedito da Germania a U.S.A.
Spedito da Germania a U.S.A.
Quantità: 1 disponibili
Foto dell'editore
Formal Equivalence Checking and Design Debugging
Print on DemandDa: Majestic Books, Hounslow, Regno Unito
Valutazione del venditore 4 su 5 stelle
Condizione: New. Print on Demand pp. 252 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam. Codice articolo 5824902
Compra nuovo
EUR 259,87
Spedizione EUR 7,50
Spedito da Regno Unito a U.S.A.
Spedito da Regno Unito a U.S.A.
Quantità: 4 disponibili
Foto dell'editore
Formal Equivalence Checking and Design Debugging
Print on DemandDa: Biblios, Frankfurt am main, HESSE, Germania
Valutazione del venditore 4 su 5 stelle
Condizione: New. PRINT ON DEMAND pp. 252. Codice articolo 183104339
Compra nuovo
EUR 265,49
Spedizione EUR 9,95
Spedito da Germania a U.S.A.
Spedito da Germania a U.S.A.
Quantità: 4 disponibili