VHDL Coding Styles and Methodologies - Rilegato

Cohen, Ben

 
9780792384748: VHDL Coding Styles and Methodologies
Rilegato
ISBN 10: 0792384741 ISBN 13: 9780792384748
Casa editrice: Springer-Verlag GmbH, 1999

Sinossi

This text follows up the first edition of the same book and also "VHDL Answers to Frequently Asked Questions", first and second editions. The book was originally written as a teaching tool for a VHDL training course. This new edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD, which also includes the GNU toolsite with EMACS language-sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology included an evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. The text is intended for professional engineers as well as students. It is organized in 13 chapters, each covering a separate aspect of the language, with complete examples. It provides a practical approach to learning VHDL. Combining methodologies and coding styles, along with VHDL rules, the text aims to lead the reader in the right direction from the beginning. Included is a CD that contains: all code included in the book; GNU EMACS language-sensitive editor with VHDL, Verilog, and templates for other languages; GNU TSHELL tools that emulate Unix shell; 30-day evaluation of ModelSim VHDL compiler/simulator from Model Technology; 20-day evaluation of Synplify VHDL/Verilog FPGA synthesizer from Synplicity; VHDL template demonstrating the language syntax; and VHDL '87 and HDL '93 formal syntax in HTML format.

Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.

Product Description

This text follows up the first edition of the same book and also "VHDL Answers to Frequently Asked Questions", first and second editions. The book was originally written as a teaching tool for a VHDL training course. This new edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD, which also includes the GNU toolsite with EMACS language-sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology included an evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. The text is intended for professional engineers as well as students. It is organized in 13 chapters, each covering a separate aspect of the language, with complete examples. It provides a practical approach to learning VHDL. Combining methodologies and coding styles, along with VHDL rules, the text aims to lead the reader in the right direction from the beginning. Included is a CD that contains: all code included in the book; GNU EMACS language-sensitive editor with VHDL, Verilog, and templates for other languages; GNU TSHELL tools that emulate Unix shell; 30-day evaluation of ModelSim VHDL compiler/simulator from Model Technology; 20-day evaluation of Synplify VHDL/Verilog FPGA synthesizer from Synplicity; VHDL template demonstrating the language syntax; and VHDL '87 and HDL '93 formal syntax in HTML format.

Contenuti

Preface. 1.0. VHDL Overview and Concepts. 2.0. Basic Language Elements. 3.0. Control Structures. 4.0. Drivers. 5.0. VHDL Timing. 6.0. Elements of Entity/Architecture. 7.0. Subprograms. 8.0. Packages. 9.0. User Defined Attributes, Specifications, and Configurations. 10.0. Design for Synthesis. 11.0. Functional Models and Testbenches. 12.0. UART Project. Appendix A: VHDL 93 and VHDL 87 Syntax Summary. Appendix B: Package Standard. Appendix C: Package Textio. Appendix D: STD_Logic_Textio. Appendix E: Package STD_Logic_1164. Appendix F: Numeric_STD. Appendix G: STD_Logic_Unsigned. Appendix H: STD_Logic_Signed. Appendix I: STD_Logic_Arith. Appendix J: STD_Logic_Misc. Appendix K: VHDL Predefined Attributes. Index.

Le informazioni nella sezione "Su questo libro" possono far riferimento a edizioni diverse di questo titolo.

Editore
Springer-Verlag GmbH
Data di pubblicazione
1999
Lingua
Inglese
ISBN 10 
0792384741
ISBN 13 
9780792384748
Rilegatura
Copertina rigida
Numero di pagine
455
Contatto del produttore
non disponibile
Persona responsabile
ProductSafety@springernature.com
ProductSafety@springernature.com

Poststr. 9
Darmstadt
64293
Germania

Altre edizioni note dello stesso titolo

9781475771886: VHDL Coding Styles and Methodologies

Edizione in evidenza

ISBN 10:  1475771886 ISBN 13:  9781475771886
Casa editrice: Springer, 2013
Brossura