Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench: The System Architect's Workbench: 85 - Rilegato

Thomas, Donald E.; Lagnese, Elizabeth D.; Walker, Robert A.; Rajan, Jayanth V.; Blackburn, Robert L.; Nestor, John A.

 
9780792390534: Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench: The System Architect's Workbench: 85

Sinossi

Such design tools hold the promise of raising the level of abstraction at which an integrated circuit is designed, thus releasing the current designers from many of the details of logic and circuit level design.

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Contenuti

1. Introduction.- 1.1. Synthesis of Integrated Circuits.- 1.2 The System Architect’s Workbench.- 1.3 Contrasting Approaches to Synthesis.- 1.4. Historical Note.- 1.5. Overview of the Book.- 2. Design Representations and Synthesis.- 2.1 The Model of Design Representation.- 2.2. Behavioral Representations at the ALGORITHMIC Level.- 2.3. Behavioral and Structural Representations at the REGISTER-TRANSFER Level.- 2.4. Modeling ALGORITHMIC and RT Level Synthesis.- 2.6 Summary.- 3. Transformations.- 3.1. Vtbody Transformations.- 3.2. SELECT Transformations.- 3.3. Adding Processes To The Workbench.- 3.4. Process Creation.- 3.5. Pipestage Creation.- 3.6. Structural Transformations.- 3.7. Summary.- 4. Architectural Partitioning (APARTY).- 4.1. Architectural Partitioning.- 4.2. Previous Work: Clustering.- 4.3. Multi-Stage Clustering.- 4.4. Methodology.- 4.5. Guiding Other Synthesis Tools.- 4.6. A Partitioning Example.- 4.7. Summary.- 5. Control Step Scheduling (CSTEP).- 5.1. The Scheduling Problem.- 5.2. Related Work.- 5.3. The CSTEP Scheduling Approach.- 5.4. Scheduling Examples.- 5.5. Summary.- 6. Data Path Allocation (EMUCS).- 6.1. Other Data Path Allocators.- 6.2. EMUCS Overview.- 6.3. Initialization.- 6.4. Prebinding and Manual Binding.- 6.5. Automatic Binding.- 6.6. Post-Processing.- 6.7. Finish Up.- 6.9. Summary.- 7. Microprocessor Synthesis (SUGAR).- 7.1. Organization of SUGAR.- 7.2. Behavioral Transformations.- 7.3. Execution Unit Organization Analysis.- 7.4. Code Generation.- 7.5. Code Selection.- 7.6. Register and Bus Assignment.- 7.7. Phase Structure of SUGAR.- 7.8. Summary.- 8. Synthesis Results.- 8.1. Fifth Order Digital Elliptic Wave Filter.- 8.2. Kalman Filter.- 8.3. BTL310.- 8.4. MCS6502.- 8.5. MC68000.- 8.6. Summary.- 9. Correlating the Multilevel Design Representation (CORAL).- 9.1 Linking Design Representations.- 9.2 Applications.- 9.3 Summary.- 10. Observations and Future Work.- 10.1. Are The Two Synthesis Paths Different?.- 10.2. You Need More Than Synthesis.- 10.3. Algorithmic Level Synthesis.- 10.4. Logic Synthesis, Module Generation and Physical Design.- 10.5. Design Languages.- 10.6. Summary.- References.

Product Description

Book by Thomas Donald E Lagnese Elizabeth D Walker Robert

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Altre edizioni note dello stesso titolo

9781461288152: Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench: The System Architect's Workbench: 85

Edizione in evidenza

ISBN 10:  1461288150 ISBN 13:  9781461288152
Casa editrice: Springer, 2011
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