Cache and Interconnect Architectures in Multiprocessors - Rilegato

Rilegato

ISBN 10: 0792390741 ISBN 13: 9780792390749

Casa editrice: SPRINGER NATURE, 1990

Riassunto

Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures.

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Contenuti

TLB Consistency and Virtual Caches.- The Cost of TLB Consistency.- Virtual-Address Caches in Multiprocessors.- Simulation and Performance Studies — Cache Coherence.- A Critique of Trace-Driven Simulation for Shared-Memory Multiprocessors.- Performance of Symmetry Multiprocessor System.- Analysis of Cache Invalidation Patterns in Shared-Memory Multiprocessors.- Memory-Access Penalties in Write-Invalidate Cache Coherence Protocols.- Performance of Parallel Loops using Alternate Cache Consistency Protocols on a Non-Bus Multiprocessor.- Predicting the Performance of Shared Multiprocessor Caches.- Cache Coherence Protocols.- The Cache Coherence Protocol of the Data Diffusion Machine.- SCI (Scalable Coherent Interface) Cache Coherence.- Interconnect Architectures.- Performance Evaluation of Wide Shared Bus Multiprocessors.- Crossbar-Multi-processor Architecture.- “CHESS” Multiprocessor—A Processor-Memory Grid for Parallel Programming.- Software Cache Coherence Schemes.- Software-directed Cache Management in Multiprocessors.

Product Description

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Dettagli dell'edizione

• Editore: SPRINGER NATURE
• Data di pubblicazione: 1990
• Lingua: Inglese
• ISBN 10: 0792390741
• ISBN 13: 9780792390749
• Rilegatura: Copertina rigida
• Numero di pagine: 277
• Redattore: Dubois Michel, Thakkar Shreekant S.
• Contatto del produttore: non disponibile
• Persona responsabile: ProductSafety@springernature.com; ProductSafety@springernature.com; ; Poststr. 9; Darmstadt; 64293; Germania