Sinossi
Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers.
High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book.
Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model.
The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.
Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.
Contenuti
1. Introduction. 2. System Overview. 3. Behavioral Transformations. 4. Sequencing Graph and Resource Model. 5. Design Space Exploration. 6. Relative Scheduling. 7. Resource Conflict Resolution. 8. Relative Control Generation. 9. Relative Control Optimization. 10. System Implementation. 11. Experimental Results. 12. Conclusions and Future Work. References. Index.
Product Description
Book by Ku David C DeMicheli Giovanni
Le informazioni nella sezione "Su questo libro" possono far riferimento a edizioni diverse di questo titolo.
Altre edizioni note dello stesso titolo
Risultati della ricerca per High Level Synthesis of Asics Under Timing and Synchronizati...
Foto dell'editore
High Level Synthesis of Asics Under Timing and Synchronization Constraints
Da: ThriftBooks-Atlanta, AUSTELL, GA, U.S.A.
Valutazione del venditore 5 su 5 stelle
Hardcover. Condizione: Fair. No Jacket. Readable copy. Pages may have considerable notes/highlighting. ~ ThriftBooks: Read More, Spend Less. Codice articolo G0792392442I5N00
Compra usato
EUR 14,27
Spedizione gratuita
Spedito in U.S.A.
Spedito in U.S.A.
Quantità: 1 disponibili
Immagini fornite dal venditore
High Level Synthesis of ASICs under Timing and Synchronization Constraints. The Kluwer International Series in Engineering and Computer Science,
Da: books4less (Versandantiquariat Petra Gros GmbH & Co. KG), Welling, Germania
Valutazione del venditore 5 su 5 stelle
gebundene Ausgabe. Condizione: Gut. 294 Seiten; Das hier angebotene Buch stammt aus einer teilaufgelösten wissenschaftlichen Bibliothek und trägt die entsprechenden Kennzeichnungen (Rückenschild, Instituts-Stempel.); Schnitt und Einband sind etwas staubschmutzig; der Buchzustand ist ansonsten ordentlich und dem Alter entsprechend gut. Text in ENGLISCHER Sprache! Sprache: Englisch Gewicht in Gramm: 700. Codice articolo 1581843
Compra usato
EUR 7,95
Spedizione EUR 15,95
Spedito da Germania a U.S.A.
Spedito da Germania a U.S.A.
Quantità: 1 disponibili
Foto dell'editore
High Level Synthesis of ASICs under Timing and Synchronization Constraints
Editore:
Kluwer Academic Publishers, Boston, 1992
ISBN 10: 0792392442
ISBN 13: 9780792392446
Antico o usato
Rilegato
Da: PsychoBabel & Skoob Books, Didcot, Regno Unito
Valutazione del venditore 5 su 5 stelle
hardcover. Condizione: Very Good. Condizione sovraccoperta: No Dust Jacket. Name from previous owner on FEP. Light surface wear to covers and slightly softened corners, though otherwise binding is very well preserved. Pages are clean and crisp, and printing is tight, clean and bright throughout. No Dust Jacket. MB. Used. Codice articolo 248464
Compra usato
EUR 34,98
Spedizione EUR 14,49
Spedito da Regno Unito a U.S.A.
Spedito da Regno Unito a U.S.A.
Quantità: 1 disponibili
Foto dell'editore
High Level Synthesis of ASICs under Timing and Synchronization Constraints (The Springer International Series in Engineering and Computer Science, 177)
Da: Ria Christie Collections, Uxbridge, Regno Unito
Valutazione del venditore 5 su 5 stelle
Condizione: New. In. Codice articolo ria9780792392446_new
Compra nuovo
EUR 164,57
Spedizione EUR 13,89
Spedito da Regno Unito a U.S.A.
Spedito da Regno Unito a U.S.A.
Quantità: Più di 20 disponibili
Immagini fornite dal venditore
High Level Synthesis of Asics Under Timing and Synchronization Constraints
Da: GreatBookPrices, Columbia, MD, U.S.A.
Valutazione del venditore 5 su 5 stelle
Condizione: New. Codice articolo 757939-n
Compra nuovo
EUR 180,88
Spedizione EUR 2,28
Spedito in U.S.A.
Spedito in U.S.A.
Quantità: 15 disponibili
Immagini fornite dal venditore
High Level Synthesis of ASICs under Timing and Synchronization Constraints
Print on DemandDa: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
Valutazione del venditore 5 su 5 stelle
Buch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis. 312 pp. Englisch. Codice articolo 9780792392446
Compra nuovo
EUR 160,49
Spedizione EUR 23,00
Spedito da Germania a U.S.A.
Spedito da Germania a U.S.A.
Quantità: 2 disponibili
Immagini fornite dal venditore
High Level Synthesis of ASICs under Timing and Synchronization Constraints
Print on DemandDa: moluna, Greven, Germania
Valutazione del venditore 5 su 5 stelle
Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constra. Codice articolo 5971358
Compra nuovo
EUR 136,16
Spedizione EUR 48,99
Spedito da Germania a U.S.A.
Spedito da Germania a U.S.A.
Quantità: Più di 20 disponibili
Immagini fornite dal venditore
High Level Synthesis of ASICs under Timing and Synchronization Constraints
Print on DemandDa: preigu, Osnabrück, Germania
Valutazione del venditore 5 su 5 stelle
Buch. Condizione: Neu. High Level Synthesis of ASICs under Timing and Synchronization Constraints | David C. Ku (u. a.) | Buch | xiv | Englisch | 1992 | Springer | EAN 9780792392446 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand. Codice articolo 102548947
Compra nuovo
EUR 141,20
Spedizione EUR 70,00
Spedito da Germania a U.S.A.
Spedito da Germania a U.S.A.
Quantità: 5 disponibili
Foto dell'editore
High Level Synthesis of ASICs under Timing and Synchronization Constraints
Da: Books Puddle, New York, NY, U.S.A.
Valutazione del venditore 4 su 5 stelle
Condizione: New. pp. 312. Codice articolo 26320299
Compra nuovo
EUR 208,23
Spedizione EUR 3,44
Spedito in U.S.A.
Spedito in U.S.A.
Quantità: 4 disponibili
Foto dell'editore
High Level Synthesis of ASICs Under Timing and Synchronization Constraints
Da: Kennys Bookshop and Art Galleries Ltd., Galway, GY, Irlanda
Valutazione del venditore 5 su 5 stelle
Condizione: New. Addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. This work also addresses specific issues in applying high-level synthesis techniques to the design of ASICs. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 294 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 19. Weight in Grams: 615. . 1992. Hardback. . . . . Codice articolo V9780792392446
Compra nuovo
EUR 201,68
Spedizione EUR 10,50
Spedito da Irlanda a U.S.A.
Spedito da Irlanda a U.S.A.
Quantità: 15 disponibili