Modeling of Electrical Overstress in Integrated Circuits: 289 - Rilegato

Diaz, Carlos H.; Sung-Mo (Steve) Kang; Duvvury, Charvaka

Rilegato

ISBN 10: 0792395050 ISBN 13: 9780792395058

Casa editrice: Springer-Verlag GmbH, 1994

Riassunto

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. This text presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behaviour up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behaviour up to the onset of thermal failure. This text should be suitable for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators should also benefit from the material covered. This book should also be of interest to researchers and first- and second-year graduate students working in semiconductor devices and IC reliability fields.

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Contenuti

List of Figures. List of Tables. Preface. 1. Electrical Overstress in ICs. 2. NMOS ESD Protection Devices and Process Related Issues. 3. Measuring EOS Robustness in ICs. 4. EOS Thermal Failure Simulation for Integrated Circuits. 5. ITSIM: a Nonlinear 2D--1D Thermal Simulator. 6. 2D Electrothermal Analysis of Device Failure in MOS Processes. 7. Circuit Level Electrothermal Simulation. 8. IETSIM: an Electrothermal Circuit Simulator. 9. Summary and Future Research. Bibliography. Index.

Product Description

Book by Diaz Carlos H SungMo Steve Kang Duvvury Charvaka

Dettagli dell'edizione

• Editore: Springer-Verlag GmbH
• Data di pubblicazione: 1994
• Lingua: Inglese
• ISBN 10: 0792395050
• ISBN 13: 9780792395058
• Rilegatura: Copertina rigida
• Numero di pagine: 178
• Contatto del produttore: ProductSafety@springernature.com; ProductSafety@springernature.com; ; Poststr. 9; Darmstadt; 64293; Germania