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Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels.
The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.
Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.
Contenuti
List of Figures. List of Tables. Preface. 1. Introduction. 2. Survey of Simulation and Macromodeling Techniques. 3. A Nonlinear Macromodel. 4. Reduction Techniques for Complex Gates. 5. Accounting for RC- Interconnects. 6. Transmission Gate Modeling. 7. Conclusions. A. The SPICE Level 2 Model. B. Nonlinear Macromodel Output Response Derivations. C. The Derivation of M = 0.5 Heuristic in Reduction Techniques. D. Delay Errors for Various AOI Gates. References. Index.
Product Description
Book by Kong JeongTaek Overhauser David V
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- EditoreKluwer Academic Pub
- Data di pubblicazione1995
- ISBN 10 0792395808
- ISBN 13 9780792395805
- RilegaturaCopertina rigida
- LinguaInglese
- Numero di pagine292
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Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing)
Editore:
Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A., 1995
ISBN 10: 0792395808
ISBN 13: 9780792395805
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hardcover. Condizione: Very Good. Condizione sovraccoperta: No Dust Jacket. First Edition. White hardcover with white lettering on spine and upper board and contents in very good clean condition, showing minimal signs of wear. Previous owner's name on FEP. Profusely illustrated by diagrams and tables. No dust jacket. T. Used. Codice articolo 249216
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Digital Timing Macromodeling for VLSI Design Verification
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Condizione: Gut. Zustand: Gut - Gebrauchs- und Lagerspuren. Außen: verschmutzt, angestoßen. Innen: Seiten verschmutzt, Geknickt. | Seiten: 292 | Sprache: Englisch | Produktart: Bücher. Codice articolo 2297973/3
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Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science, 319)
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Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science, 319)
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Gebunden. Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timi. Codice articolo 5971598
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Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. Codice articolo 9780792395805
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Digital Timing Macromodeling for VLSI Design Verification
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Buch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. 292 pp. Englisch. Codice articolo 9780792395805
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Digital Timing Macromodeling for VLSI Design Verification
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Condizione: New. pp. 292 Index. Codice articolo 26319980
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Digital Timing Macromodeling for VLSI Design Verification
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Condizione: New. PRINT ON DEMAND pp. 292. Codice articolo 18319974
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Digital Timing Macromodeling for VLSI Design Verification
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Condizione: New. Print on Demand pp. 292 Figures, 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam. Codice articolo 7560755
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