Logic Synthesis and Verification Algorithms - Rilegato

Hachtel, Gary D.; Somenzi, Fabio

Rilegato

ISBN 10: 0792397460 ISBN 13: 9780792397465

Casa editrice: Kluwer Academic Pub, 1996

Riassunto

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

Su questo libro

Product Description

This textbook is designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. This book is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

Contenuti

I: Introduction. 1. Introduction. 2. A Quick Tour of Logic Synthesis with the Help of a Simple Example. II: Two Level Logic Synthesis. 3. Boolean Algebras. 4. Synthesis of Two-Level Circuits. 5. Heuristic Minimization of Two-Level Circuits. 6. Binary Decision Diagrams (BDDs) III: Models of Sequential Systems. 7. Models of Sequential Systems. 8. Synthesis and Verification of Finite State Machines. 9. Finite Automata. IV: Multilevel Logic Synthesis. 10. Multi-Level Logic Synthesis. 11. Multi-Level Minimization. 12. Automatic Test Generation for Combinational Circuits. 13. Technology Mapping. A. ASCII Codes. B. Supplementary Problems. Bibliography. Index.

Dettagli dell'edizione

• Editore: Kluwer Academic Pub
• Data di pubblicazione: 1996
• Lingua: Inglese
• ISBN 10: 0792397460
• ISBN 13: 9780792397465
• Rilegatura: Copertina rigida
• Numero di pagine: 564
• Contatto del produttore: Springer-Verlag GmbH; customerservice@springernature.com; ; Tiergartenstraße 17; Heidelberg; Baden-Württemberg; 69121; Germania