Testing and Testable Design of High-Density Random-Access Memories presents an integrated approach to state-of-the-art testing and testable design techniques for RAMs. These new techniques are being used for increasing the memory testability and for lowering the cost of test equipment. Semiconductor memories are an essential component of digital computers - they are used as primary storage devices. For the past two decades there has been vigorous research in semiconductor memory design and testing. Such research has resulted in bringing the dynamic RAM (DRAM) to the forefront of the microelectronics industry in terms of achievable integration levels, high performance, high reliability, low power and low cost. The DRAM is regarded as the technological driver of the commercial microelectronics industry.
Testing and Testable Design of High-Density Random-Access Memories is written primarily for the practicing design engineer and the manufacturer of random-access memories (RAMs). It provides useful exposure to state-of-the-art testing schemes and testable design approaches for RAMs. It is also useful as a supplementary text for undergraduate courses on testing and testability of RAMs.
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List of Figures. List of Tables. About the Authors. Foreword. Preface. Symbols and Notation. 1. Introduction. 2. Electrical Testing of Faults. 3. Functional Fault Modeling and Testing. 4. Technology and Layout-Related Testing. 5. Built-In Self-Testing and Design for Testability. 6. Conclusion. A: Glossary. B: Commercial RAM Data. C: Market for RAMs. References. Index.
Book by Mazumder Pinaki Chakraborty Kanad
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