Retargetable Code Generation for Digital Signal Processors - Rilegato

Leupers, Rainer

Rilegato

ISBN 10: 0792399587 ISBN 13: 9780792399582

Casa editrice: Kluwer Academic Publishers, 1997

Riassunto

The market for consumer electronics is characterized by rapidly growing complexities of applications and decreasing market window opportunities. A key concept for coping with such requirements is the reuse of system components. Embedding programmable processors into VLSI systems facilitates reuse and offers a high degree of flexibility. The use of embedded processors, however, poses challenges for software compilers, because real-time constraints and limited silicon area for program memories demand extremely efficient machine code. Additionally there is a need for flexible, retargetable compilers which explore the mutual dependence between processor architectures and program execution speed. Current compiler technology does not meet these demands, particularly the area of DSP where application-specific processors are predominant. As a consequence, the largest part of DSP software is still developed manually at assembly language level. Recent research efforts, located at the intersection of software and hardware design, aim at eliminating this bottleneck. Retargetable Code Generation for Digital Signal Processors outlines the new role of compilers in hardware/software codesign of embedded systems, and it describes the state-of-the-art in the area of retargetable code generation and optimization for embedded DSPs. It presents concepts and algorithmic solutions, which achieve both retargetability and high code quality. In contrast to approaches taken in classical compiler construction, emphasis is put on effective code optimization instead of high compilation speed. The usefulness of the proposed techniques is demonstrated for real-life architectures. This volume presents an integrated solution for retargetable DSP compilers. It covers the whole compilation process, including target processor modelling, intermediate code generation, code selection, register allocation, scheduling and optimization for parallelism. It should be of interest to researchers, senior design engineers and CAD managers both in academia and industry.

Su questo libro

Contenuti

Foreword. Preface. 1. Introduction. 2. Processor Modelling. 3. Instruction-Set Extraction. 4. Code Generation. 5. Instruction-Level Parallelism. 6. The Record Compiler. 7. Conclusions. References. Index.

Dettagli dell'edizione

• Editore: Kluwer Academic Publishers
• Data di pubblicazione: 1997
• Lingua: Inglese
• ISBN 10: 0792399587
• ISBN 13: 9780792399582
• Rilegatura: Copertina rigida
• Numero di pagine: 220
• Contatto del produttore: Springer-Verlag GmbH; customerservice@springernature.com; ; Tiergartenstraße 17; Heidelberg; Baden-Württemberg; 69121; Germania