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The IEEE International Workshop on Defect and Fault Tolerance in Vlsi Systems: Proceedings : November 13-15, 1995 Lafayette, Louisiana - Rilegato
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An invited talk recounts Intel's experience with increasing die yield through CAD algorithms, and a panel discussion examines tools for the extracting of critical areas for a yield analysis of VLSI design. Others of the 34 papers cover critical area analysis, defect sensitivity and reliability, fault tolerant architectures and arrays, yield projection and enhancement, fault tolerant and testing techniques, and self-checking and coding techniques. No subject index. Annotation copyright Book News, Inc. Portland, Or.
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- EditoreIEEE Computer Society
- Data di pubblicazione1995
- ISBN 10 0818671076
- ISBN 13 9780818671074
- RilegaturaCopertina rigida
- LinguaInglese
- Numero di pagine305
- Contatto del produttorenon disponibile
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The IEEE international workshop on Defect & Fault-Tolerance in VLSI Systems, Proceedings, 1995.
Editore:
IEEE Computer Society Press, Los Alamitos, 1995
ISBN 10: 0818671076
ISBN 13: 9780818671074
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Rilegato
Da: Lost and Found Books, Healesville, VIC, Australia
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hard cover. No Jacket. Illustrated in black and white. 305 pages VG. Slight shelf wear to covers, overall very good condition. Codice articolo 13953
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