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Fault and Defect Tolerant Computer Architectures
Editore:
Creative Media Partners, LLC, 2025
ISBN 10: 1025140540
ISBN 13: 9781025140544
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Da: PBShop.store US, Wood Dale, IL, U.S.A.
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HRD. Condizione: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Codice articolo L1-9781025140544
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Fault and Defect Tolerant Computer Architectures
Editore:
Creative Media Partners, LLC, 2025
ISBN 10: 1025140540
ISBN 13: 9781025140544
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Da: PBShop.store UK, Fairford, GLOS, Regno Unito
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HRD. Condizione: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Codice articolo L1-9781025140544
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Fault and Defect Tolerant Computer Architectures
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Condizione: New. Print on Demand. Codice articolo 408331644
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Fault and Defect Tolerant Computer Architectures
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Condizione: New. PRINT ON DEMAND. Codice articolo 18404822697
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Fault and Defect Tolerant Computer Architectures
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Condizione: New. Print on Demand. Codice articolo 26404822691
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Fault and Defect Tolerant Computer Architectures (Hardcover)
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Hardcover. Condizione: new. Hardcover. As conventional silicon Complementary Metal-Oxide-Semiconductor (CMOS) technology continues to shrink, logic circuits are increasingly subject to errors in- duced by electrical noise and cosmic radiation. In addition, the smaller devices are more likely to degrade and fail in operation. In the long term, new device technolo- gies such as quantum cellular automata and molecular crossbars may replace silicon CMOS, but they have significant reliability problems. Rather than requiring the cir- cuit to be defect-free, fault tolerance techniques incorporated into an architecture allow continued system operation in the presence of faulty components. This research addresses construction of a reliable computer from unreliable de- vice technologies. A system architecture is developed for a "fault and defect tolerant" (FDT) computer. Trade-offs between different techniques are studied, and the yield of the system is modelled. Yield and hardware cost models are developed for the fault tolerance techniques used in the architecture. Fault and defect tolerant designs are created for the processor, and its most critical component, the cache memory.This work has been selected by scholars as being culturally important, and is part of the knowledge base of civilization as we know it. This work was reproduced from the original artifact, and remains as true to the original work as possible. Therefore, you will see the original copyright references, library stamps (as most of these works have been housed in our most important libraries around the world), and other notations in the work.This work is in the public domain in the United States of America, and possibly other nations. Within the United States, you may freely copy and distribute this work, as no entity (individual or corporate) has a copyright on the body of the work.As a reproduction of a historical artifact, this work may contain missing or blurred pages, poor pictures, errant marks, etc. Scholars believe, and we concur, that this work is important enough to be preserved, reproduced, and made generally available to the public. We appreciate your support of the preservation process, and thank you for being an important part of keeping this knowledge alive and relevant. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability. Codice articolo 9781025140544
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Fault and Defect Tolerant Computer Architectures
Editore:
Creative Media Partners, LLC Mai 2025, 2025
ISBN 10: 1025140540
ISBN 13: 9781025140544
Nuovo
Rilegato
Da: AHA-BUCH GmbH, Einbeck, Germania
Valutazione del venditore 5 su 5 stelle
Buch. Condizione: Neu. Neuware - As conventional silicon Complementary Metal-Oxide-Semiconductor (CMOS) technology continues to shrink, logic circuits are increasingly subject to errors in- duced by electrical noise and cosmic radiation. In addition, the smaller devices are more likely to degrade and fail in operation. In the long term, new device technolo- gies such as quantum cellular automata and molecular crossbars may replace silicon CMOS, but they have significant reliability problems. Rather than requiring the cir- cuit to be defect-free, fault tolerance techniques incorporated into an architecture allow continued system operation in the presence of faulty components. This research addresses construction of a reliable computer from unreliable de- vice technologies. A system architecture is developed for a 'fault and defect tolerant' (FDT) computer. Trade-offs between different techniques are studied, and the yield of the system is modelled. Yield and hardware cost models are developed for the fault tolerance techniques used in the architecture. Fault and defect tolerant designs are created for the processor, and its most critical component, the cache memory. Codice articolo 9781025140544
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