Closing the Gap Between Asic & Custom: Tools and Techniques for High-Performance Asic Design - Rilegato

Chinnery, David; Keutzer, Kurt William

Rilegato

ISBN 10: 1402071132 ISBN 13: 9781402071133

Casa editrice: Kluwer Academic Pub, 2002

Riassunto

by Kurt Keutzer Those looking for a quick overview of the book should fast-forward to the Introduction in Chapter 1. What follows is a personal account of the creation of this book. The challenge from Earl Killian, formerly an architect of the MIPS processors and at that time Chief Architect at Tensilica, was to explain the significant performance gap between ASICs and custom circuits designed in the same process generation. The relevance of the challenge was amplified shortly thereafter by Andy Bechtolsheim, founder of Sun Microsystems and ubiquitous investor in the EDA industry. At a dinner talk at the 1999 International Symposium on Physical Design, Andy stated that the greatest near-term opportunity in CAD was to develop tools to bring the performance of ASIC circuits closer to that of custom designs. There seemed to be some synchronicity that two individuals so different in concern and character would be pre-occupied with the same problem. Intrigued by Earl and Andy s comments, the game was afoot. Earl Killian and other veterans of microprocessor design were helpful with clues as to the sources of the performance discrepancy: layout, circuit design, clocking methodology, and dynamic logic. I soon realized that I needed help in tracking down clues. Only at a wonderful institution like the University of California at Berkeley could I so easily commandeer an ab- bodied graduate student like David Chinnery with a knowledge of architecture, circuits, computer-aided design and algorithms.

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Recensione

From the reviews:
"This book unveils the mystery behind the performance gap between ASIC and Custom design and shows how to close the gap with minimal design effort. A must read for every ASIC or ASSP designer."
(William J. Dally, Professor, Stanford University)
"Most IP core providers must provide high-performance designs within the constraints of an ASIC methodology. I'm optimistic that careful application of the techniques in this book will enable me to design embedded processors that do indeed close `the Gap Between ASIC and Custom'."
(Kees Vissers, Director of Architecture, Trimedia Technologies Inc.)
"This book provides a comprehensive explanation of why ASICs fall so far behind custom ICs in performance, and then shows how better tools, libraries and methodologies can narrow the gap. It's a must read for ASIC designers who want to boost performance - or custom designers who want to speed time to market with ASIC-like design methodologies."
(Richard Goering, EDA Editorial Director, EE Times)
"I've heard there is a price on the authors' heads. Power Users don't like people who give away their secrets."
(Gary Smith, Chief Analyst, Dataquest)
"This book reflects the best research to date on understanding the tradeoffs between full-custom intellectual property blocks and synthesized intellectual-property blocks - a topic we could only touch on in the Reuse Methodology Manual. It is required reading for anyone engaged in system-on-a-chip design."
(Michael Keating, author of the Reuse Methodology Manual, Vice-President, Synopsys)
"Solves one of life's little mysteries[...] It looks like it should become required reading for the IC innovators of this millennium."
(Neil Weste, author of Principles of CMOS VLSI Design, Cisco Systems, Inc.)

Contenuti

Preface. List of trademarks. 1. Introduction and Overview of the Book; D. Chinnery, K. Keutzer. Contributing Factors. 2. Improving Performance through Microarchitecture; D. Chinnery, K. Keutzer. 3. Reducing the Timing Overhead; D. Chinnery, K. Keutzer. 4. High-Speed Logic, Circuits, Libraries and Layout; A. Chang, et al. 5. Finding Peak Performance in a Process; D. Chinnery, K. Keutzer. Design Techniques. 6. Physical Prototyping Plans for High Performance; M. Courtoy, et al. 7. Automatic Replacement of Flip-Flops by Latches in ASIC's; D. Chinnery, et al. 8. Useful-Skew Clock Synthesis Boosts ASIC Performance; W. Dai, D. Staepelaere. 9. Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing; M. Côté, P. Hurat. 10. Design Optimization with Automated Flex-Cell Creation; D. Bhattacharya, V. Boppana. 11. Exploiting Structure and Managing Wires to Increase Density and Performance; A. Chang, W.J. Dally. 12. Semi-Custom Methods in a High-Performance Microprocessor Design; G.A. Northrop. 13. Controlling Uncertainty in High Frequency Designs; S.E. Rich, et al. 14. Increasing Circuit Performance through Statistical Design Techniques; M. Orshansky. Design Examples. 15. Achieving 550MHz in a Standard Cell ASIC Methodology; D. Chinnery, et al. 16. The iCORE® 520MHz Synthesizable CPU Core; N. Richardson, et al. 17. Creating Synthesizable ARM Processors with Near Custom Performance; D. Flynn, M.Keating.

Dettagli dell?edizione

• Editore: Kluwer Academic Pub
• Data di pubblicazione: 2002
• Lingua: Inglese
• ISBN 10: 1402071132
• ISBN 13: 9781402071133
• Rilegatura: Copertina rigida
• Numero di pagine: 432
• Contatto del produttore: Springer Nature Customer Service Center GmbH; ProductSafety@springernature.com