Sinossi
Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control.
The different chapters of Power Aware Design Methodologies have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful.
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Contenuti
Contributors. Preface. 1. Introduction; M. Pedram, J. Rabaey. 2. CMOS Device Technology Trends for Power-Constrained Applications; D.J. Frank. 3. Low Power Memory Design; Y. Oowaki, T. Tanzawa. 4. Low-Power Digital Circuit Design; T. Kuroda. 5. Low Voltage Analog Design; K. Uyttenhove, M. Steyaert. 6. Low Power Flip-Flop and Clock Networks Design Methodologies in High-Performance System-On-A-Chip; C. Kim, S.-M.S. Kang 7. Power Optimization by Datapath Width Adjustment; H. Yasuura, H. Tomiyama. 8. Energy-Efficient Design of High-Speed Links; G.-Y. Wei, et al. 9. System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing; D. Marculescu, R. Marculescu. 10. Tools and Techniques for Integrated Hardware-Software Energy Optimizations; N. Vijaykrishnan, et al. 11. Power-Aware Communication Systems; M. Srivastava. 12. Power-Aware Wireless Microsensor Networks; R. Min, et al. 13. Circuit and System Level Power Management; F. Fallah, M. Pedram. 14. Tools and Methodologies for Power Sensitive Design; J. Frenkil. 15. Reconfigurable Processors - The Road to Flexible Power-Aware Computing; J. Rabaey, et al. Index.
Product Description
Book by Pedram Massoud Rabaey Jan M
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Gebunden. Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and arch. Codice articolo 4094867
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Buch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control.The different chapters of Power Aware Design Methodologies have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful. 546 pp. Englisch. Codice articolo 9781402071522
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Buch. Condizione: Neu. Power Aware Design Methodologies | Jan M. Rabaey (u. a.) | Buch | xx | Englisch | 2002 | Springer US | EAN 9781402071522 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand. Codice articolo 102417487
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Condizione: New. Presenting various aspects of power-aware design methodologies, this book covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits. Num Pages: 522 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 30. Weight in Grams: 940. . 2002. Hardback. . . . . Codice articolo V9781402071522
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