Articoli correlati a Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits:...
Sinossi
This book is essential to understand new test methodologies, algorithms and industrial practices. Without its insight into the physics of nano-metric technologies, it would be difficult to develop system-level test strategies that yield a high IC fault coverage. The work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. The 2nd edition of Defect Oriented Testing has been extensively updated with the addition of chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering to provide a link between defect sources and yield. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.
Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.
Dalla quarta di copertina
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts.
The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.
Le informazioni nella sezione "Su questo libro" possono far riferimento a edizioni diverse di questo titolo.
Compra nuovo
Visualizza questo articolo
EUR 159,03
EUR 13,79 per la spedizione da Regno Unito a U.S.A.
Destinazione, tempi e costiAltre edizioni note dello stesso titolo
Risultati della ricerca per Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits:...
Foto dell'editore
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing, 34)
Da: Ria Christie Collections, Uxbridge, Regno Unito
Valutazione del venditore 5 su 5 stelle
Condizione: New. In. Codice articolo ria9781441942852_new
Quantità: Più di 20 disponibili
Foto dell'editore
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing, 34)
Da: Lucky's Textbooks, Dallas, TX, U.S.A.
Valutazione del venditore 5 su 5 stelle
Condizione: New. Codice articolo ABLIING23Mar2411530295755
Quantità: Più di 20 disponibili
Immagini fornite dal venditore
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Print on DemandDa: moluna, Greven, Germania
Valutazione del venditore 4 su 5 stelle
Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Wide coverage of topics in test engineeringUnique defect-oriented focus of the materialsIntroduction to yield engineering common practicesThe 2nd edition of defect oriented testing has been extensively updated. New cha. Codice articolo 4174637
Quantità: Più di 20 disponibili
Foto dell'editore
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Paperback)
Editore:
Springer-Verlag New York Inc., New York, NY, 2010
ISBN 10: 1441942858
ISBN 13: 9781441942852
Nuovo
Paperback
Da: Grand Eagle Retail, Bensenville, IL, U.S.A.
Valutazione del venditore 5 su 5 stelle
Paperback. Condizione: new. Paperback. Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Codice articolo 9781441942852
Quantità: 1 disponibili
Immagini fornite dal venditore
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Editore:
Springer US, Springer New York Nov 2010, 2010
ISBN 10: 1441942858
ISBN 13: 9781441942852
Nuovo
Taschenbuch
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
Valutazione del venditore 5 su 5 stelle
Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent. 352 pp. Englisch. Codice articolo 9781441942852
Quantità: 2 disponibili
Immagini fornite dal venditore
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Editore:
Springer US, Springer New York Nov 2010, 2010
ISBN 10: 1441942858
ISBN 13: 9781441942852
Nuovo
Taschenbuch
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germania
Valutazione del venditore 5 su 5 stelle
Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 352 pp. Englisch. Codice articolo 9781441942852
Quantità: 1 disponibili
Immagini fornite dal venditore
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Editore:
Springer US, Springer New York, 2010
ISBN 10: 1441942858
ISBN 13: 9781441942852
Nuovo
Taschenbuch
Da: AHA-BUCH GmbH, Einbeck, Germania
Valutazione del venditore 5 su 5 stelle
Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent. Codice articolo 9781441942852
Quantità: 1 disponibili
Foto dell'editore
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Da: Revaluation Books, Exeter, Regno Unito
Valutazione del venditore 5 su 5 stelle
Paperback. Condizione: Brand New. 2nd edition. 349 pages. 9.10x6.10x0.90 inches. In Stock. Codice articolo x-1441942858
Quantità: 2 disponibili
Foto dell'editore
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing (34))
Da: Mispah books, Redhill, SURRE, Regno Unito
Valutazione del venditore 4 su 5 stelle
Paperback. Condizione: Like New. Like New. book. Codice articolo ERICA78714419428586
Quantità: 1 disponibili
Foto dell'editore
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Paperback)
Editore:
Springer-Verlag New York Inc., New York, NY, 2010
ISBN 10: 1441942858
ISBN 13: 9781441942852
Nuovo
Paperback
Da: AussieBookSeller, Truganina, VIC, Australia
Valutazione del venditore 5 su 5 stelle
Paperback. Condizione: new. Paperback. Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability. Codice articolo 9781441942852
Quantità: 1 disponibili