Low Power Methodology Manual: For System-on-Chip Design - Brossura

Flynn, David; Aitken, Rob; Gibbons, Alan; Shi, Kaijian

Brossura

ISBN 10: 1441944184 ISBN 13: 9781441944184

Casa editrice: Springer, 2011

Riassunto

This book provides a practical guide for engineers doing low power System-on-Chip (SoC) designs. It covers various aspects of low power design from architectural issues and design techniques to circuit design of power gating switches. It also describes some well established techniques and then details the latest approaches to low power design. These leading edge techniques include power gating and adaptive voltage scaling. In addition to providing a theoretical basis for these techniques, the book addresses the practical issues of implementing them in today's designs with today's tools. All of the methods used have been proven in test chips jointly developed by Synopsys and ARM.

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Informazioni sull?autore

<p><strong>ABOUT THE AUTHORS:</strong></p><p><strong>Michael Keating</strong> is a Synopsys Fellow in the company’s Advanced Technology Group, focusing on IP development methodology, hardware and software design quality and low power design.</p><p></p><p><strong>David Flynn</strong> is an ARM R&amp;D Fellow and has been with the company since 1991, specializing in low power System-on-Chip IP deployment and methodology.</p><p></p><p><strong>Robert Aitken</strong> is an ARM R&amp;D Fellow. His areas of responsibility include memory architecture, design for testability and design for manufacturability.</p><p></p><p><strong>Alan Gibbons</strong> is a Principal Engineer at Synopsys, with a focus on development of advanced methodology and technology for ARM processor-based system design.</p><p></p><p><strong>Kaijian Shi</strong> is a Principal Consultant in the Professional Services Group of Synopsys, specializing in low power design methodology and implementation.</p>

Dalla quarta di copertina

<p><em>"Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach."</em> </p><p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<strong> Richard Goering</strong>, Software Editor, EE Times</p><p></p><p><em>"Excellent compendium of low-power techniques and guidelines with&nbsp;balanced content spanning theory and practical implementation. The LPMM is&nbsp;a very welcome addition to the field of low power SoC implementation that&nbsp;has for many years operated in a largely ad-hoc fashion."</em> </p><p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<strong>&nbsp; Sujeeth Joseph</strong>, Chief Architect - Semiconductor &amp; <br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Systems Solutions Unit, Wipro Technologies<br><br><em>"The LPMM enables broader adoption of aggressive power management techniques&nbsp; based &nbsp;on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs"</em></p><p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <strong>Anil Mankar</strong>, Sr VP&nbsp; Worldwide Core Engineering&nbsp;<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;and&nbsp;Chief Development Officer, Conexant Systems Inc.</p><p><em>"Managing power, at 90nm and below, introduces significant challenges to design flow.&nbsp; The LPMM is a timely and immediately useful book that shows how combination of tools, IP and methodology can be used together to address power management."</em></p><p><strong>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Nick Salter,</strong> Head of Chip Integration, CSR plc.</p><p></p><p><strong>ABOUT THE AUTHORS:</strong></p><p><strong>Michael Keating</strong> is a Synopsys Fellow in the company’s Advanced Technology Group, focusing on IP development methodology, hardware and software design quality and low power design.</p><p></p><p><strong>David Flynn</strong> is an ARM R&amp;D Fellow and has been with the company since 1991, specializing in low power System-on-Chip IP deployment and methodology.</p><p></p><p><strong>Robert Aitken</strong> is an ARM R&amp;D Fellow. His areas of responsibility include memory architecture, design for testability and design for manufacturability.</p><p></p><p><strong>Alan Gibbons</strong> is a Principal Engineer at Synopsys, with a focus on development of advanced methodology and technology for ARM processor-based system design.</p><p></p><p><strong>Kaijian Shi</strong> is a Principal Consultant in the Professional Services Group of Synopsys, specializing in low power design methodology and implementation.</p>

Dettagli dell?edizione

• Editore: Springer
• Data di pubblicazione: 2011
• Lingua: Inglese
• ISBN 10: 1441944184
• ISBN 13: 9781441944184
• Rilegatura: Copertina flessibile
• Numero di pagine: 320
• Contatto del produttore: Springer Nature Customer Service Center GmbH; ProductSafety@springernature.com