The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.
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Preface. Part I: Low-Power Low-Voltage. Introduction. Low-Power Low-Voltage Limitations and Prospects in Analog Design; E.A. Vittoz. Design Considerations for High-Speed Low-Power Low-Voltage CMOS Analog-to-Digital Converters; T.B. Cho, D.W. Cline, C.S.G. Conroy, P.R. Gray. Micro-Power Analog-Filter Design; G. Groenewold, B. Monna, B. Nauta. Low Power Oversampled A/D Converters; E. Dijkstra, O. Nys, E. Blumenkrantz. Low Voltage Low Power Design Techniques for Medical Devices; D.A. Wayne. Part II: Integrated Filters. Introduction. Developments in Integrated Continuous Time Filters; Y. Tsividis. Analog Integrated Polyphase Filters; M. Steyaert, J. Crols. Transconductor-C Filters; J.M. Khoury. Recent Advances in Switched-Current Filters; J.B. Hughes, K.W. Moulding. Switched Capacitor Filters; R.C.J. Taylor. Current-Mode Continuous-Time Filters; D.J. Allstot, R.H. Zele. Part III: Smart Power. Introduction. Modeling of Transient Heating in Smart Power Applications; L. Borucki. Smart Power Circuits for Power Switches including Diagnostic Functions; H. Zitta. Design and Circuit Techniques of Integrated Switching Voltage Regulators; T. Szepesi. High Voltage ICs for Mains Applications; F. Schoofs. DMOS Transistors in Smart Power Building Blocks; B. Graindourze. Design Methodologies for Mixed Power Integrated Circuits; B. Murari. Slide Supplement.
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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of 'analog clock cycles' required to produce one effective output sample of the signal being quantized. 412 pp. Englisch. Codice articolo 9781441951496
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Taschenbuch. Condizione: Neu. Neuware -The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of 'analog clock cycles' required to produce one effective output sample of the signal being quantized.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 412 pp. Englisch. Codice articolo 9781441951496
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Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of 'analog clock cycles' required to produce one effective output sample of the signal being quantized. Codice articolo 9781441951496
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