Formal verification means having a mathematical model of a system, a language for specifying desired properties of the system in a concise, comprehensible and unambiguous way, and a method of proof to verify that the specified properties are satisfied. When the method of proof is carried out substantially by machine, we speak of automatic verification. Symbolic Model Checking deals with methods of automatic verification as applied to computer hardware.
The practical motivation for study in this area is the high and increasing cost of correcting design errors in VLSI technologies. There is a growing demand for design methodologies that can yield correct designs on the first fabrication run. Moreover, design errors that are discovered before fabrication can also be quite costly, in terms of engineering effort required to correct the error, and the resulting impact on development schedules. Aside from pure cost considerations, there is also a need on the theoretical side to provide a sound mathematical basis for the design of computer systems, especially in areas that have received little theoretical attention.
Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.
Foreword. Preface. 1. Introduction. 2. Model Checking. 3. Symbolic Model Checking. 4. The SMV System. 5. A Distributed Cache Protocol. 6. Mu-Calculus Model Checking. 7. Induction and Model Checking. 8. Equivalence Computations. 9. A Partial Order Apporach. 10. Conclusion. References. Index.
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Condizione: Good. This is an ex-library book and may have the usual library/used-book markings inside.This book has soft covers. In good all round condition. Please note the Image in this listing is a stock photo and may not match the covers of the actual item,400grams, ISBN:9781461363996. Codice articolo 4345489
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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Formal verification means having a mathematical model of a system, a language for specifying desired properties of the system in a concise, comprehensible and unambiguous way, and a method of proof to verify that the specified properties are satisfied. When the method of proof is carried out substantially by machine, we speak of automatic verification. Symbolic Model Checking deals with methods of automatic verification as applied to computer hardware. The practical motivation for study in this area is the high and increasing cost of correcting design errors in VLSI technologies. There is a growing demand for design methodologies that can yield correct designs on the first fabrication run. Moreover, design errors that are discovered before fabrication can also be quite costly, in terms of engineering effort required to correct the error, and the resulting impact on development schedules. Aside from pure cost considerations, there is also a need on the theoretical side to provide a sound mathematical basis for the design of computer systems, especially in areas that have received little theoretical attention. 216 pp. Englisch. Codice articolo 9781461363996
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