Sinossi
Integrated circuit densities and operating speeds continue to rise at an exponential rate. Chips, however, cannot get larger and faster without a sharp decrease in power consumption beyond the current levels. Minimization of power consumption in VLSI chips has thus become an important design objective. In fact, with the explosive growth in demand for portable electronics and the usual push toward more complex functionality and higher performance, power consumption has in many cases become the limiting factor in satisfying the market demand.
A new generation of power-conscious CAD tools are coming onto the market to help designers estimate, optimize and verify power consumption levels at most stages of the IC design process. These tools are especially prevalent at the register-transfer level and below. There is a great need for similar tools and capabilities at the behavioral and system levels of the design process. Many researchers and CAD tool developers are working on high-level power modeling and estimation, as well as power-constrained high-level synthesis and optimization. Techniques and tools alone are, however, insufficient to optimize VLSI circuit power dissipation - a consistent and convergent design methodology is also required.
Power Optimization and Synthesis at Behavioral and System Levels Using Formal Methods was written to address some of the key problems in power analysis and optimization early in the design process. In particular, this book focuses on power macro-modeling based on regression analysis and power minimization through behavioral transformations, scheduling, resource assignment and hardware/software partitioning and mapping. What differentiates this book from other published work on the subject is the mathematical basis and formalism behind the algorithms and the optimality of these algorithms subject to the stated assumptions.
From the Foreword:
`This book makes animportant contribution to the field of system design technologies by presenting a set of algorithms with guaranteed optimality properties, that can be readily applied to system-level design. This contribution is timely, because it fills the need of new methods for a new design tool generation, which supports the design of electronic systems with even more demanding requirements'.
Giovanni De Micheli, Professor, Stanford University
Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.
Contenuti
List of Figures. List of Tables. Preface. 1. Introduction. 2. Register Allocation and Binding. 3. Power-Optimal Module Allocation and Binding. 4. Multiple Supply Voltage Scheduling. 5. Co-Design of Communicating Systems. 6. Conclusion. References. Index.b
Product Description
Book by Chang JuiMing Pedram Massoud
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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Integrated circuit densities and operating speeds continue to rise at an exponential rate. Chips, however, cannot get larger and faster without a sharp decrease in power consumption beyond the current levels. Minimization of power consumption in VLSI chips has thus become an important design objective. In fact, with the explosive growth in demand for portable electronics and the usual push toward more complex functionality and higher performance, power consumption has in many cases become the limiting factor in satisfying the market demand. A new generation of power-conscious CAD tools are coming onto the market to help designers estimate, optimize and verify power consumption levels at most stages of the IC design process. These tools are especially prevalent at the register-transfer level and below. There is a great need for similar tools and capabilities at the behavioral and system levels of the design process. Many researchers and CAD tool developers are working on high-level power modeling and estimation, as well as power-constrained high-level synthesis and optimization. Techniques and tools alone are, however, insufficient to optimize VLSI circuit power dissipation - a consistent and convergent design methodology is also required. Power Optimization and Synthesis at Behavioral and System Levels Using Formal Methods was written to address some of the key problems in power analysis and optimization early in the design process. In particular, this book focuses on power macro-modeling based on regression analysis and power minimization through behavioral transformations, scheduling, resource assignment and hardware/software partitioning and mapping. What differentiates this book from other published work on the subject is the mathematical basis and formalism behind the algorithms and the optimality of these algorithms subject to the stated assumptions. From the Foreword: `This book makes an important contribution to the field of system design technologies by presenting a set of algorithms with guaranteed optimality properties, that can be readily applied to system-level design. This contribution is timely, because it fills the need of new methods for a new design tool generation, which supports the design of electronic systems with even more demanding requirements'. Giovanni De Micheli, Professor, Stanford University 196 pp. Englisch. Codice articolo 9781461373681
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Taschenbuch. Condizione: Neu. Power Optimization and Synthesis at Behavioral and System Levels Using Formal Methods | Jui-Ming Chang (u. a.) | Taschenbuch | Einband - flex.(Paperback) | Englisch | 2012 | Springer Us | EAN 9781461373681 | Verantwortliche Person für die EU: Springer Heidelberg, Tiergartenstr. 17, 69121 Heidelberg, buchhandel-buch[at]springer[dot]com | Anbieter: preigu. Codice articolo 105997410
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Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - Integrated circuit densities and operating speeds continue to rise at an exponential rate. Chips, however, cannot get larger and faster without a sharp decrease in power consumption beyond the current levels. Minimization of power consumption in VLSI chips has thus become an important design objective. In fact, with the explosive growth in demand for portable electronics and the usual push toward more complex functionality and higher performance, power consumption has in many cases become the limiting factor in satisfying the market demand. A new generation of power-conscious CAD tools are coming onto the market to help designers estimate, optimize and verify power consumption levels at most stages of the IC design process. These tools are especially prevalent at the register-transfer level and below. There is a great need for similar tools and capabilities at the behavioral and system levels of the design process. Many researchers and CAD tool developers are working on high-level power modeling and estimation, as well as power-constrained high-level synthesis and optimization. Techniques and tools alone are, however, insufficient to optimize VLSI circuit power dissipation - a consistent and convergent design methodology is also required. Power Optimization and Synthesis at Behavioral and System Levels Using Formal Methods was written to address some of the key problems in power analysis and optimization early in the design process. In particular, this book focuses on power macro-modeling based on regression analysis and power minimization through behavioral transformations, scheduling, resource assignment and hardware/software partitioning and mapping. What differentiates this book from other published work on the subject is the mathematical basis and formalism behind the algorithms and the optimality of these algorithms subject to the stated assumptions. From the Foreword: `This book makes animportant contribution to the field of system design technologies by presenting a set of algorithms with guaranteed optimality properties, that can be readily applied to system-level design. This contribution is timely, because it fills the need of new methods for a new design tool generation, which supports the design of electronic systems with even more demanding requirements'. Giovanni De Micheli, Professor, Stanford University. Codice articolo 9781461373681
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