Sinossi
List of Figures. List of Tables. Preface. 1. Introduction. 2. VLSI Systems. 3. Signal Delay in VLSI Systems. 4. Timing Properties of Synchronous Systems. 5. Clock Scheduling and Clock Tree Synthesis. 6. Clock Scheduling for Improved Reliability. 7. Practical Considerations. 8. Experimental Results. 9. Conclusions. 10. Future Directions. References. Appendices. Index. About the Authors.
Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.
