Sinossi
Preface. 1.0. VHDL Overview and Concepts. 2.0. Basic Language Elements. 3.0. Control Structures. 4.0. Drivers. 5.0. VHDL Timing. 6.0. Elements of Entity/Architecture. 7.0. Subprograms. 8.0. Packages. 9.0. User Defined Attributes, Specifications, and Configurations. 10.0. Design for Synthesis. 11.0. Functional Models and Testbenches. 12.0. UART Project. Appendix A: VHDL 93 and VHDL 87 Syntax Summary. Appendix B: Package Standard. Appendix C: Package Textio. Appendix D: STD_Logic_Textio. Appendix E: Package STD_Logic_1164. Appendix F: Numeric_STD. Appendix G: STD_Logic_Unsigned. Appendix H: STD_Logic_Signed. Appendix I: STD_Logic_Arith. Appendix J: STD_Logic_Misc. Appendix K: VHDL Predefined Attributes. Index.
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