CMOS - MEMS: 2 - Rilegato

Rilegato

ISBN 10: 3527310800 ISBN 13: 9783527310807

Casa editrice: Vch Verlagsgesellschaft Mbh, 2005

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Microstructures, electronics, nanotechnology - these vast fields of research are growing together as the size gap narrows and many different materials are combined. Current research, engineering sucesses and newly commercialized products hint at the immense innovative potentials and future applications that open up once mankind controls shape and function from the atomic level right up to the visible world without any gaps. Sensor systems, microreactors, nanostructures, nanomachines, functional surfaces, integrated optics, displays, communications technology, biochips, human/machine interfaces, prosthetics, miniaturized medical and surgery equipment and many more opportunities are being explored. This new series, Advanced Micro and Nano Systems, provides cutting-edge reviews from top authors on technologies, devices and advanced systems from the micro and nano worlds.

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Informazioni sull?autore

Henry Baltes is Professor of Physical Electronics at ETH Zurich since 1988. He is the Director of the Physical Electronics Laboratory active in CMOS-based bioelectronic, chemical, and physical micro and nano sensor systems and a co-founder of the spin-off company SENSIRION. He held visiting appointments at Stanford University, the University of Waterloo, Ritsumeikan University, the University of Bologna, and the University of Freiburg. Prior to 1988, he held the Henry Marshall Tory Chair at the University of Alberta, where he was Acting President of the Alberta Microelectronics Centre and co-founder and Director of LSI Logic Corporation of Canada. From 1974 to 1982 he worked for Landis & Gyr Zug (now Siemens) Switzerland, where he directed the solid-state device laboratory. He received the D. Sc. degree from ETH Zurich in 1971. Henry Baltes is a Fellow of the IEEE and a Member of the Swiss Academy of Technical Sciences. He received the European Science Award of the Koerber Foundation, the Wilhelm Exner Medal of the Austrian Trade Association, and honorary doctoral degrees of the University of Waterloo and the Alma Mater Studiorum University of Bologna. Oliver Brand is an Associate Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology, Atlanta, USA. He received his diploma degree in Physics from Technical University Karlsruhe, Germany in 1990, and his Ph.D. degree (Doctor of Natural Sciences) from ETH Zurich, Switzerland in 1994. Between 1995 and 2002, he held research and teaching positions at the Georgia Institute of Technology (1995-1997) and ETH Zurich (1997-2002). Dr. Brand has co-authored more than 100 publications in scientific journals and conference proceedings and two books. His research interest is in the areas of CMOS-based micro- and nanosystems, MEMS fabrication technologies, and microsystem packaging. Dr. Brand is on the editorial board of Sensors and Materials and has served on the program committees of a number of conferences, including MEMS and Eurosensors. Gary K. Fedder is a Professor at Carnegie Mellon University where he holds a joint appointment with the Department of Electrical and Computer Engineering and the Robotics Institute. He received the B.S. and M.S. degrees in electrical engineering from MIT in 1982 and 1984, respectively. From 1984 to 1989, he worked at Hewlett-Packard on a VLSI IC tester and on modeling printed-circuit-board interconnect for high-speed computers. He received his Ph.D. in 1994 from U.C. Berkeley, successfully demonstrating the first microstructure with sigma-delta multi-mode electrostatic servo control. He is a subject editor for IEEE J. MEMS and on the editorial board of IoP J. Micromech. and Microengineering. Professor Fedder's research interests include microelectromechanical systems (MEMS) modeling, simulation and synthesis, integration of MEMS and CMOS, microsensor design, microactuator control systems, and probe-based data storage. Christofer Hierold holds the Chair of Micro- and Nanosystems at the ETH in Zurich, Switzerland, since April 2002. Prior to that, he spent eleven years with Siemens AG and Infineon Technologies AG, responsible for R&D on microsystems, advanced CMOS processes, memories, nanoelectronics and new materials. During his time in industry, his major research and development achievements were in the field of CMOS compatible microsystems, such as fully integrated, surface micromachined intelligent CMOS pressure sensors and fingertip sensors. His current research work focuses on the evaluation of new materials for MEMS, on advanced microsystems and on nanotransducers. Professor Hierold holds numerous patents and has published over 20 research articles in peer reviewed journals and international conference proceedings. He served on the program committees of several scientific conferences, MEMS and IEDM amongst others, and is also in the International Steering Committee of the European Conference on Solid-State Transducers. Jan G. Korvink holds a Chair for Microsystem Technology at Albert Ludwig University in Freiburg, Germany, where he runs the laboratory for microsystem simulation and also serves as the Dean of the Faculty of Applied Science. Prior to that, he worked at the Physical Electronics Lab, Institute for Quantum Electronics of the ETH Zurich, where he built up and led the microsystem modelling effort. Three of the MEMS simulation programs that were developed by him and his group during this time were successfully commercialized. He has co-authored more than 100 papers in scientific journals and conference digests, as well as numerous book chapters and a book on semiconductors for engineers. He stayed at Ritsumeikan University in Shiga, Japan, and the ETH Zurich as visiting professor, served as European editor for Sensors and Materials and on both the IEE MEMS and IEEE IEDM committees. Professor Korvink currently serves on the committees of a number of conferences related to MEMS, including Eurosensors, DTIP, ESSDERC, and the MSM. His research interests cover the modeling and simulation of microsystems and the low cost fabrication of polymer-based MEMS. Osamu Tabata received his M.S. and Ph.D. degrees from Nagoya Institute of Technology, Nagoya, Japan, in 1981 and in 1993, respectively. From 1981 to 1996, he performed industrial research at Toyota Central Research and Development Laboratories, Inc., in Aichi, Japan. In 1996, he joined the Department of Mechanical Engineering of Ritsumeikan University in Shiga, Japan. He spent three months each as Guest Professor at the Institute of Microsystem Technology, Freiburg University, Germany, in 2000 and at ETH Zurich, Switzerland, in 2001. In September 2003, he joined the Department of Mechanical Engineering, Kyoto University, Kyoto, Japan. Professor Tabata is currently engaged in the research of micro/nano processes, the LIGA process, MEMS and micro/nano system synthetic engineering (SENS). He serves as an associate editor of J. MEMS and is on the editorial boards of several journals, and a program committee member of numerous international conferences. He was honored with the Science News Award in 1987, Presentation Paper Award in 1992, and received the R&D 100 Award in 1993 and 1998.

Dalla quarta di copertina

Advanced Micro & Nanosystems (AMN) provides cutting-edge reviews and detailed case studies by top authors from science and industry, covering technologies, devices and advanced systems from the micro and nano worlds, which together have an immense innovative application potential that opens up with control of shape and function from the atomic level right up to the visible world without any technological gaps. In this topical volume, the combination of the globally established, billion dollar chip mass fabrication technology CMOS with the fascinating and commercially promising new world of MEMS is covered from all angles. The book introduces readers to this field and takes them from fabrication technologies and material charaterization aspects to the actual applications of CMOS-MEMS - a wide range of miniaturized physical, chemical and biological sensors and RF systems. Vital knowledge on circuit and system integration issues concludes this in-depth treatise, illustrating the advantages of combining CMOS and MEMS in the first place, rather than having a hybrid solution.

Dal risvolto di copertina interno

Advanced Micro & Nanosystems (AMN) provides cutting-edge reviews and detailed case studies by top authors from science and industry, covering technologies, devices and advanced systems from the micro and nano worlds, which together have an immense innovative application potential that opens up with control of shape and function from the atomic level right up to the visible world without any technological gaps.

In this topical volume, the combination of the globally established, billion dollar chip mass fabrication technology CMOS with the fascinating and commercially promising new world of MEMS is covered from all angles.
The book introduces readers to this field and takes them from fabrication technologies and material charaterization aspects to the actual applications of CMOS-MEMS - a wide range of miniaturized physical, chemical and biological sensors and RF systems. Vital knowledge on circuit and system integration issues concludes this in-depth treatise, illustrating the advantages of combining CMOS and MEMS in the first place, rather than having a hybrid solution.

Estratto. � Ristampato con autorizzazione. Tutti i diritti riservati.

CMOS-MEMS

Advanced Micro and Nanosystems, Volume 2

John Wiley & Sons

Copyright � 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
All right reserved.
ISBN: 978-3-527-31080-7

Chapter One

Fabrication Technology

O. Brand, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA

Abstract

This chapter provides an overview on fabrication technologies for CMOS-based microelectromechanical systems (MEMS). The first part briefly introduces the basic microfabrication steps, highlights a CMOS process sequence and how CMOS materials can be used for microsystems design. While a number of microsystems can be fabricated within the regular CMOS process sequence, the focus of the chapter is on combining CMOS technology with micromachining process modules. CMOS-compatible bulk and surface micromachining techniques are introduced in the second part of the chapter together with an overview of the design challenges faced when combining mechanical microstructures and electronics on the same substrate. The micromachining modules can either precede (pre-CMOS), follow (post-CMOS) or be performed in between (intra-CMOS) the regular CMOS process steps. The last part of the chapter provides an extensive overview on the different CMOS-based MEMS approaches found in the literature.

Keywords

Micromachining; CMOS-based MEMS; MEMS fabrication; microsystem fabrication

1.1 CMOS Technology 2 1.1.1 Basic Microfabrication Steps 4 1.1.1.1 Thin Film Deposition 5 1.1.1.2 Patterning 6 1.1.1.3 Etching 8 1.1.1.4 Doping 9 1.1.2 CMOS Process Sequence 9 1.1.3 CMOS Materials for Micro- and Nanosystems 11 1.1.4 CMOS Microsystems 14 1.2 CMOS-compatible Micromachining Process Modules 17 1.2.1 Bulk Micromachining 18 1.2.2 Surface Micromachining 22 1.3 CMOS-compatible Design of MEMS and NEMS 23 1.3.1 Tolerable Process Modifications 24 1.3.2 Design Rule Modifications 26 1.3.3 Simulation of Circuitry and MEMS 27 1.4 CMOS and Micromachining 28 1.4.1 Pre-CMOS Micromachining 33 1.4.2 Intra-CMOS Micromachining 37 1.4.3 Post-CMOS Micromachining 43 1.4.3.1 Post-CMOS Micromachining of Add-on Layers 43 1.4.3.2 Post-CMOS Micromachining of CMOS Layers 49 1.5 Conclusion 56 1.6 References 57

1.1 CMOS Technology

State-of-the-art CMOS processes, such as IBM's 9S2 process based on SOI (silicon-on-insulator) technology on 300 mm wafers, feature a minimal physical gate length of less than 100 nm and up to eight (copper) metallization levels (see Fig. 1.1,). Such advanced CMOS processes are required for the fabrication of today's and tomorrow's microprocessors comprising tens of millions of transistors on a single chip. An example is Apple Computer's 64-bit PowerPC-G5 processor with more than 58 million transistors, manufactured using IBM's 90nm CMOS technology.

Researchers at IBM's T.J. Watson Research Center have recently used the copper-based interconnect technology of such modern CMOS processes to fabricate microelectromechanical devices, namely r.f. switches and resonators. Up to now, however, most commercially available microsystems combining (micromachined) transducer elements and integrated electronics on a single chip rely on CMOS or BiCMOS processes with minimum feature sizes typically between 0.5 and 3 m and 4 or 6 in wafer sizes. While the underlying CMOS technologies are between 10 and 15 years old, their capabilities are sufficient for most microsystem applications. An example is the pressure sensor KP100 by Infineon Technologies, a surface micromachined pressure sensor array with on-chip circuitry for signal conditioning, A/D conversion, calibration and system diagnostic, which is based on a 0.8 m BiCMOS technology on 6 in wafers.

A typical cross-section of a sub-m (0.5-1.0 m) CMOS technology used for CMOS-based microelectromechanical systems (MEMS) is shown in Fig. 1.2. The twin-well technology is based on 6 in p-type wafers and uses a polysilicon/silicide gate, low-doped drain (LDD) technology for source and drain formation, silicide source/drain contacts and a two-level metallization based on tungsten plugs and aluminum interconnects. A thermal oxide separates adjacent transistors, chemical vapor deposition (CVD) silicon dioxide layers are used as dielectric layers between the metallization levels and a PECVD (plasma enhanced CVD) silicon nitride layer or a silicon dioxide, silicon nitride sandwich are employed as passivation layer. The CMOS fabrication sequence is briefly highlighted in Section 1.1.2. More detailed process descriptions can be found in a number of microelectronics textbooks, e.g.

When designing CMOS-based MEMS or microsystems, the designer must adhere, to a great extent, to the chosen CMOS process sequence in order not to sacrifice the functionality of the on-chip electronics. This limits the available 'design space' for the integrated microsystems, as e.g. materials, material properties and layer thicknesses are determined by the CMOS process. In the following, a brief introduction into integrated circuit fabrication will be given: the basic fabrication steps are highlighted (Section 1.1.1) and a CMOS process sequence is summarized (Section 1.1.2). Section 1.1.3 discusses how the different CMOS materials and layers can be used in micro- and nanosystems and Section 1.1.4 depicts a few microsystems that can be completely formed within a regular CMOS sequence.

1.1.1 Basic Microfabrication Steps

The fabrication of integrated circuits (ICs) using CMOS or BiCMOS technology is based on four basic microfabrication techniques: deposition, patterning, doping and etching. Fig. 1.3 illustrates how these techniques are combined to build up an IC layer by layer: a thin film, such as an insulating silicon dioxide film, is deposited on the substrate, a silicon wafer. A light-sensitive photoresist layer is then deposited on top and patterned using photolithography. Finally, the pattern is transferred from the photoresist layer to the silicon dioxide layer by an etching process. After removing the remaining photoresist, the next layer is deposited and structured, and so on. Doping of a semiconductor material by ion implantation, the key step for the fabrication of diodes and transistors, can be performed directly after photolithography, i.e. using a photoresist layer as mask, or after patterning an implantation mask (e.g. a silicon dioxide layer).

Silicon is the standard substrate material for IC fabrication and, hence, the most common substrate material in microfabrication in general. It is supplied as single-crystal wafers with diameters between 100 and 300 mm. In addition to its favorable electrical properties, single-crystal silicon also has excellent mechanical properties, which enable the design of micromechanical structures. CMOS processes for digital electronics typically use low-doped (doping concentration in the [10.sup.16] [cm.sup.-3] range) silicon wafers, whereas processes for mixed-signal or analog electronics are often based on high-doped (doping concentration in the [10.sup.19] [cm.sup.-3] range) wafers with a low-doped epitaxial layer to minimize latch-up. The choice of the substrate material might already require a compromise between the requirements for the MEMS part and the on-chip electronics: the fabrication of membrane structures for, e.g., pressure sensors is typically based on anisotropic silicon etching in a potassium hydroxide (KOH) solution (see Section 1.2). High p-type doping ([N.sub.A] [greater than or equal to] [10.sup.19] [cm.sup.-3]) substantially reduces the silicon etch rates in KOH solutions, thus preventing the use of highly p-doped CMOS substrates in combination with KOH etching.

In the following, a brief overview on the four basic microfabrication steps will be given. More details can be found in textbooks and reference books on semiconductor processing.

1.1.1.1 Thin-film Deposition

The two most common thin-film deposition methods in microfabrication are chemical vapor deposition (CVD), performed at low pressure (LPCVD), atmospheric pressure (APCVD) or plasma-enhanced (PECVD), and physical vapor deposition (PVD), such as sputtering and evaporating. Typical CVD and PVD film thicknesses are in the range of tenths of nanometers up to a few micrometers. Other film deposition techniques include electroplating of metal films (e.g. the copper metallization in state-of-the-art CMOS processes) and spin- or spray-coating of polymeric films such as photoresist. Both processes can yield film thicknesses from less than 1 m up to several hundreds of micrometers.

Dielectric layers, predominantly silicon dioxide, Si[O.sub.2], and silicon nitride, Si[N.sub.x], are used as insulating material, as mask material and for device passivation. Silicon dioxide is either thermally grown on top of a silicon surface (thermal oxide) at high temperatures (900-1200 C) in an oxidation furnace or it is deposited in a CVD system (CVD oxide). CVD oxides can be deposited at temperatures between 300 and 900C, with the high-temperature depositions usually yielding better film properties. Low-temperature CVD oxide films are typically deposited in PECVD systems and high-temperature CVD oxide films in LPCVD equipment. Silicon nitride layers deposited in LPCVD furnaces are commonly used as masking material during local oxidation of silicon (LOCOS process), while PECVD silicon nitride films are used for e.g. device passivation.

Highly doped polycrystalline silicon (polysilicon) is used as gate material for metal oxide semiconductor field effect transistors (MOSFETs), as electrode and resistor materials, for piezoresistive sensing structures, as thermoelectric material, and for thermistors. Polysilicon microstructures released by sacrificial layer etching are also widely used in sensor applications (see Section 1.4). Polysilicon is usually deposited in an LPCVD furnace using silane (Si[H.sub.4]) as gaseous precursor.

Metal layers are used, e.g., for electrical interconnects, as electrode material, for resistive temperature sensors (thermistors) or as mirror surfaces. Metals, which are widely used in the microelectronics industry, such as aluminum, titanium and tungsten, are routinely deposited by sputtering. Depending on the application, a large number of other metals, including gold, palladium, platinum, silver or alloys, can be deposited with PVD methods. A number of metals and metal compounds, such as Cu, W[Si.sub.2], Ti[Si.sub.2], TiN and W, can be deposited by CVD. Metal CVD processes are less common, but can provide improved step coverage or local deposition of metals. Whereas aluminum has been the standard metallization in IC fabrication for many years, the state-of-the-art sub-0.25 m CMOS technologies often feature copper as interconnect material, owing to its lower resistivity and higher electromigration resistance as compared with aluminum. An example is IBM's interconnect metallizations based on the so-called damascene process, which employ copper films electroplated in a dielectric mold. After each metallization step, planarization is achieved with a chemical-mechanical polishing (CMP) step.

Polymers such as photoresist are commonly deposited by spin- or spray-coating. Polymers can be used as dielectric materials, passivation layers, and as chemically sensitive layers for chemical and biosensors (see also Chapter 7).

1.1.1.2 Patterning

Photolithography is the standard process to transfer a pattern, which has been designed with computer-aided-engineering (CAE) software packages, on to a certain material. The process sequence is illustrated in Fig. 1.4. A mask with the desired pattern is created. The mask is a glass plate with a patterned opaque layer (typically chromium) on the surface. Electron-beam lithography is used to write the mask pattern from the CAE data. In the photolithographic process, a photoresist layer (photostructurable polymer) is spin-coated on to the material to be patterned. Next, the photoresist layer is exposed to ultraviolet (UV) light through the mask. This step is done in a mask aligner, in which mask and wafer are aligned with each other before the subsequent exposure step is performed. Depending on the mask aligner generation, mask and substrate are brought in contact or close proximity (contact and proximity printing) or the image of the mask is projected (projection printing) on to the photoresist-coated substrate. Depending on whether positive or negative photoresist was used, the exposed or the unexposed photoresist areas, respectively, are removed during the resist development process. The remaining photoresist acts as a protective mask during the subsequent etching process, which transfers the pattern onto the underlying material. Alternatively, the patterned photoresist can be used as a mask for a subsequent ion implantation. After the etching or ion implantation step, the remaining photoresist is removed, and the next layer can be deposited and patterned.

The so-called lift-off technique is used to structure a thin-film material, which would be difficult to etch. Here, the thin-film material is deposited on top of the patterned photoresist layer. In order to avoid a continuous film, the thickness of the deposited film must be less than the resist thickness. By removing the underneath photoresist, the thin-film material on top is also removed by 'lifting it off', leaving a structured thin film on the substrate.

Thick photostructurable polymer layers, such as SU-8, can be used as a mold for electroplating metal structures. A thick polymer layer is deposited on top of a metallic seed layer and photostructured. During the subsequent electroplating process, the metal is only deposited in the areas where the seed layer is exposed to the plating solution, i.e. the polymer layer acts as a plating mold.

Recently, microcontact printing or soft lithography has been introduced as an additional method for pattern transfer. A soft polymeric stamp is used to reproduce a desired pattern directly on a substrate. Routinely, feature sizes on the order of 1 m can be achieved with this technique. The polymer stamp, often made from poly(dimethylsiloxane) (PDMS), is formed by a molding process using a master fabricated with conventional microfabrication techniques. After 'inking' the stamp with the material to be printed, the stamp is brought in contact with the substrate material, and the pattern of the stamp is reproduced. Surface properties of the substrate can therefore be modified to, e.g., locally promote or prevent molecule adhesion. Soft lithography has been specifically developed for biological applications such as patterning cells or proteins with the help of, e.g., self-assembled monolayers (SAMs).

1.1.1.3 Etching

The two different categories of etching processes include wet etching using liquid chemicals and dry etching using gas-phase chemistry. Both methods can be either isotropic, i.e. provide the same etch rate in all directions, or anisotropic, i.e. provide different etch rates in different directions (see Fig. 1.5). The important criteria for selecting a particular etching process encompass the material etch rate, the selectivity for the material to be etched, and the isotropy/anisotropy of the etching process. An overview on various etching chemistries used in microfabrication can be found in.

Wet etching is usually isotropic with the important exception of anisotropic silicon wet etching in, e.g., alkaline solutions, such as potassium hydroxide (see Section 1.2). Moreover, wet etching typically provides a better etch selectivity for the material to be etched in comparison with neighboring other materials. An example includes wet etching of silicon dioxide using hydrofluoric acid-based chemistries. Si[O.sub.2] is isotropically etched in dilute hydrofluoric acid (HF-[H.sub.2]O) or buffered oxide etch, BOE (HF-N[H.sub.4]F). Typical etch rates for high-quality (thermally grown) silicon dioxide films are 0.1 m/min in BOE.

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