Graph Reduction: Proceedings of a Workshop Santa Fe, New Mexico, USA, September 29 - October 1, 1986: 279 - Brossura

Keller, Robert M.; Fasel, Joseph H.

Brossura

ISBN 10: 3540184201 ISBN 13: 9783540184201

Casa editrice: Springer, 2008

Riassunto

This volume describes recent research in graph reduction and related areas of functional and logic programming, as reported at a workshop in 1986. The papers are based on the presentations, and because the final versions were prepared after the workshop, they reflect some of the discussions as well. Some benefits of graph reduction can be found in these papers: - A mathematically elegant denotational semantics - Lazy evaluation, which avoids recomputation and makes programming with infinite data structures (such as streams) possible - A natural tasking model for fine-to-medium grain parallelism. The major topics covered are computational models for graph reduction, implementation of graph reduction on conventional architectures, specialized graph reduction architectures, resource control issues such as control of reduction order and garbage collection, performance modelling and simulation, treatment of arrays, and the relationship of graph reduction to logic programming.

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Contenuti

On the correspondence of lambda style reduction and combinator style reduction.- Head order reduction: A graph reduction scheme for the operational lambda calculus.- A simple abstract machine to execute supercombinators.- Concurrent term rewriting as a model of computation.- Alfalfa: Distributed graph reduction on a hypercube multiprocessor.- Parallel graph reduction on a supercomputer: A status report.- Target code generation from G-machine code.- Toward the design of a parallel graph reduction machine the MaRS project.- The parallel graph reduction machine, ALICE.- Overview of Rediflow II development.- Specification of reduction strategies in term rewriting systems.- Controlling reduction partial order in functional parallel programs.- Parallel garbage collection for graph machines.- Graph reduction in a parallel virtual memory environment.- Performance measurement of a G-machine implementation.- A flexible architectural study methodology.- Arrays, non-determinism, side-effects, and parallelism: A functional perspective.- A new array operation.- I-Structures: Data structures for parallel computing.- Parallel execution of an equational language.- Implementing logical variables on a graph reduction architecture.- Functional logic languages part I.- Unification of quantified terms.

Dettagli dell?edizione

• Editore: Springer
• Data di pubblicazione: 2008
• Lingua: Inglese
• ISBN 10: 3540184201
• ISBN 13: 9783540184201
• Rilegatura: Copertina flessibile
• Numero di pagine: 472
• Contatto del produttore: non disponibile
• Persona responsabile: CMN Printpool Inh. Mathis Neumann; https://www.also.com/ec/cms5/en_6000/6000/index.jsp; ; Friedrich-Karl-Str. 9; Hamburg; Germania