Articoli correlati a Higher-Level Hardware Synthesis: 2963
Sinossi
In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in?uential article published by Electronics Magazine in 1965, Moore predicted that this trend would continue for the next 10 years. Despite being criticized for its “unrealistic optimism,” Moore’s prediction has remained valid for far longer than even he imagined: today, chips built using state-- the-art techniques typically contain several million transistors. The advances in fabrication technology that have supported Moore’s law for four decades have fuelled the computer revolution. However,this exponential increase in transistor density poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available. In this monograph we investigate both (i) the design of high-level languages for hardware description, and (ii) techniques involved in translating these hi- level languages to silicon. We propose SAFL, a ?rst-order functional language designedspeci?callyforbehavioralhardwaredescription,anddescribetheimp- mentation of its associated silicon compiler. We show that the high-level pr- erties of SAFL allow one to exploit program analyses and optimizations that are not employed in existing synthesis systems. Furthermore, since SAFL fully abstracts the low-leveldetails of the implementation technology, we show how it can be compiled to a range of di?erent design styles including fully synchronous design and globally asynchronous locally synchronous (GALS) circuits.
Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.
Contenuti
1. Introduction.- 1. Introduction.- 2. Related Work.- 3. The SAFL Language.- 4. Soft Scheduling.- 5. High-Level Synthesis of SAFL.- 6. Analysis and Optimisation of Intermediate Code.- 7. Dealing with I/O.- 8. Combining Behaviour and Structure.- 9. Transformation of SAFL Specifications.- 10. Case Study.- 11. Conclusions and Further Work.
Le informazioni nella sezione "Su questo libro" possono far riferimento a edizioni diverse di questo titolo.
- EditoreSpringer
- Data di pubblicazione2008
- ISBN 10 3540213066
- ISBN 13 9783540213062
- RilegaturaCopertina flessibile
- LinguaInglese
- Numero di pagine212
- Contatto del produttorenon disponibile
Compra nuovo
Visualizza questo articolo
EUR 48,37
EUR 9,70 per la spedizione da Germania a Italia
Destinazione, tempi e costi
Risultati della ricerca per Higher-Level Hardware Synthesis: 2963
Immagini fornite dal venditore
Higher-Level Hardware Synthesis: 2963 (Lecture Notes in Computer Science, 2963)
Da: WeBuyBooks, Rossendale, LANCS, Regno Unito
Valutazione del venditore 5 su 5 stelle
Condizione: Like New. Most items will be dispatched the same or the next working day. An apparently unread copy in perfect condition. Dust cover is intact with no nicks or tears. Spine has no signs of creasing. Pages are clean and not marred by notes or folds of any kind. Codice articolo wbs8800593816
Quantità: 1 disponibili
Immagini fornite dal venditore
Higher-level hardware synthesis.
Da: Emile Kerssemakers ILAB, Heerlen, Paesi Bassi
Valutazione del venditore 5 su 5 stelle
23 cm. original paperback. 196 pp. references. index. "Lecture Notes in Computer Science". -(libr labels, otherwise (very) good). 335g. Codice articolo 71738
Quantità: 1 disponibili
Immagini fornite dal venditore
Higher-Level Hardware Synthesis
Print on DemandDa: moluna, Greven, Germania
Valutazione del venditore 5 su 5 stelle
Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in?uential article published by Electronics Magazine in 1965, Moore predicted that this. Codice articolo 4885118
Quantità: Più di 20 disponibili
Immagini fornite dal venditore
Higher-Level Hardware Synthesis
Editore:
Springer Berlin Heidelberg Mrz 2004, 2004
ISBN 10: 3540213066
ISBN 13: 9783540213062
Nuovo
Taschenbuch
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
Valutazione del venditore 5 su 5 stelle
Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in uential article published by Electronics Magazine in 1965, Moore predicted that this trend would continue for the next 10 years. Despite being criticized for its 'unrealistic optimism,' Moore's prediction has remained valid for far longer than even he imagined: today, chips built using state-- the-art techniques typically contain several million transistors. The advances in fabrication technology that have supported Moore's law for four decades have fuelled the computer revolution. However,this exponential increase in transistor density poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available. In this monograph we investigate both (i) the design of high-level languages for hardware description, and (ii) techniques involved in translating these hi- level languages to silicon. We propose SAFL, a rst-order functional language designedspeci callyforbehavioralhardwaredescription,anddescribetheimp- mentation of its associated silicon compiler. We show that the high-level pr- erties of SAFL allow one to exploit program analyses and optimizations that are not employed in existing synthesis systems. Furthermore, since SAFL fully abstracts the low-leveldetails of the implementation technology, we show how it can be compiled to a range of di erent design styles including fully synchronous design and globally asynchronous locally synchronous (GALS) circuits. 216 pp. Englisch. Codice articolo 9783540213062
Quantità: 2 disponibili
Immagini fornite dal venditore
Higher-Level Hardware Synthesis
Editore:
Springer Berlin Heidelberg, 2004
ISBN 10: 3540213066
ISBN 13: 9783540213062
Nuovo
Taschenbuch
Da: AHA-BUCH GmbH, Einbeck, Germania
Valutazione del venditore 5 su 5 stelle
Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in uential article published by Electronics Magazine in 1965, Moore predicted that this trend would continue for the next 10 years. Despite being criticized for its 'unrealistic optimism,' Moore's prediction has remained valid for far longer than even he imagined: today, chips built using state-- the-art techniques typically contain several million transistors. The advances in fabrication technology that have supported Moore's law for four decades have fuelled the computer revolution. However,this exponential increase in transistor density poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available. In this monograph we investigate both (i) the design of high-level languages for hardware description, and (ii) techniques involved in translating these hi- level languages to silicon. We propose SAFL, a rst-order functional language designedspeci callyforbehavioralhardwaredescription,anddescribetheimp- mentation of its associated silicon compiler. We show that the high-level pr- erties of SAFL allow one to exploit program analyses and optimizations that are not employed in existing synthesis systems. Furthermore, since SAFL fully abstracts the low-leveldetails of the implementation technology, we show how it can be compiled to a range of di erent design styles including fully synchronous design and globally asynchronous locally synchronous (GALS) circuits. Codice articolo 9783540213062
Quantità: 1 disponibili
Immagini fornite dal venditore
Higher-Level Hardware Synthesis
ISBN 10: 3540213066
ISBN 13: 9783540213062
Nuovo
Taschenbuch
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germania
Valutazione del venditore 5 su 5 stelle
Taschenbuch. Condizione: Neu. Neuware -In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in uential article published by Electronics Magazine in 1965, Moore predicted that this trend would continue for the next 10 years. Despite being criticized for its ¿unrealistic optimism,¿ Moore¿s prediction has remained valid for far longer than even he imagined: today, chips built using state-- the-art techniques typically contain several million transistors. The advances in fabrication technology that have supported Moore¿s law for four decades have fuelled the computer revolution. However,this exponential increase in transistor density poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available. In this monograph we investigate both (i) the design of high-level languages for hardware description, and (ii) techniques involved in translating these hi- level languages to silicon. We propose SAFL, a rst-order functional language designedspeci callyforbehavioralhardwaredescription,anddescribetheimp- mentation of its associated silicon compiler. We show that the high-level pr- erties of SAFL allow one to exploit program analyses and optimizations that are not employed in existing synthesis systems. Furthermore, since SAFL fully abstracts the low-leveldetails of the implementation technology, we show how it can be compiled to a range of di erent design styles including fully synchronous design and globally asynchronous locally synchronous (GALS) circuits.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 216 pp. Englisch. Codice articolo 9783540213062
Quantità: 2 disponibili
Foto dell'editore
Higher-Level Hardware Synthesis
Da: GreatBookPrices, Columbia, MD, U.S.A.
Valutazione del venditore 5 su 5 stelle
Condizione: New. Codice articolo 2546237-n
Quantità: Più di 20 disponibili
Foto dell'editore
Higher-Level Hardware Synthesis
Da: Ria Christie Collections, Uxbridge, Regno Unito
Valutazione del venditore 5 su 5 stelle
Condizione: New. In. Codice articolo ria9783540213062_new
Quantità: Più di 20 disponibili
Foto dell'editore
Higher-Level Hardware Synthesis
Da: GreatBookPricesUK, Woodford Green, Regno Unito
Valutazione del venditore 5 su 5 stelle
Condizione: New. Codice articolo 2546237-n
Quantità: Più di 20 disponibili
Immagini fornite dal venditore
Higher-Level Hardware Synthesis
Da: GreatBookPrices, Columbia, MD, U.S.A.
Valutazione del venditore 5 su 5 stelle
Condizione: As New. Unread book in perfect condition. Codice articolo 2546237
Quantità: Più di 20 disponibili