Field-Programmable Logic and Application: Reconfigurable Computing Is Going Mainstream : 12th International Conference, Fpl 2002, Montpellier, France, September 2-4, 2002 : Proceedings: 2438 - Brossura

International Conference On Field-Programmable Logic And Applications (12th : 2002 : Montpellier, France)

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ISBN 10: 3540441085 ISBN 13: 9783540441083

Casa editrice: Springer Nature, 2002

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Contenuti

Keynote Address.- The Age of Adaptive Computing Is Here.- Trends.- Disruptive Trends by Data-Stream-Based Computing.- Multithreading for Logic-Centric Systems.- Rapid Prototyping.- Fast Prototyping with Co-operation of Simulation and Emulation.- How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project.- FPGA Synthesis.- Implementing Asynchronous Circuits on LUT Based FPGAs.- A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations.- Custom Computing Engines.- Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems.- iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications.- Field-Programmable Custom Computing Machines - A Taxonomy -.- DSP Applications 1.- Embedded Reconfigurable Logic Core for DSP Applications.- Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard.- FPGA QAM Demodulator Design.- Reconfigurable Fabrics.- Analytical Framework for Switch Block Design.- Modular, Fabric-Specific Synthesis for Programmable Architectures.- On Optimum Designs of Universal Switch Blocks.- Dynamic Reconfiguration 1.- Improved Functional Simulation of Dynamically Reconfigurable Logic.- Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology.- Dynamic Reconfiguration in Mobile Systems.- Using PARBIT to Implement Partial Run-Time Reconfigurable Systems.- DSP Applications 2.- Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs.- Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models.- FPGA Implementation of the Wavelet Packet Transform for High Speed Communications.- A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits™.- Routing & Placement.- Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices.- Rapid and Reliable Routability Estimation for FPGAs.- Integrated Iterative Approach to FPGA Placement.- TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs.- Dynamic Reconfiguration 2.- High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices.- High Speed Homology Search Using Run-Time Reconfiguration.- Partially Reconfigurable Cores for Xilinx Virtex.- On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs.- Power Estimation.- A Flexible Power Model for FPGAs.- A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs.- Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor.- A Tool for Activity Estimation in FPGAs.- Synthesis Issues.- FSM Decomposition for Low Power in FPGA.- Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search.- A Prolog-Based Hardware Development Environment.- Fly — A Modifiable Hardware Compiler.- Keynote Address.- Challenges and Opportunities for FPGA Platforms.- Communication Applications 1.- Design and Implementation of FPGA Circuits for High Speed Network Monitors.- Granidt: Towards Gigabit Rate Network Intrusion Detection Technology.- New Technologies.- Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques.- Field-Programmable Analog Arrays: A Floating—Gate Approach.- Reconfigurable Architectures.- A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model.- A Framework for Teaching (Re)Configurable Architectures in Student Projects.- Communication Applications 2.- Specialized Hardware for Deep Network Packet Filtering.- Implementation of a Successive Erasure BCH (16,7,6) Decoder and Performance Simulation by Rapid Prototyping.- Fast RNS FPL-based Communications Receiver Design and Implementation.- Multimedia Applications.- UltraSONIC: A Reconfigurable Architecture for Video Image Processing.- Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA.- Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA.- FPGA-based Arithmetic 1.- Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices.- Automating Customisation of Floating-Point Designs.- Energy-Efficient Matrix Multiplication on FPGAs.- Reconfigurable Processors.- Run-Time Adaptive Flexible Instruction Processors.- DARP — A Digital Audio Reconfigurable Processor.- System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors.- An FPGA Based SHA-256 Processor.- Testing & Fault-Toloerance.- Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension.- On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs.- Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs.- Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs.- FPGA-based Arithmetic 2.- Logarithmic Number System and Floating-Point Arithmetics on FPGA.- Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture.- Morphable Multipliers.- A Library of Parameterized Floating-Point Modules and Their Use.- Reconfigurable Systems.- Wordlength as an Architectural Parameter for Reconfigurable Computing Devices.- An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms.- Introducing ReConfigME: An Operating System for Reconfigurable Computing.- Efficient Metacomputation Using Self-Reconfiguration.- Image Processing.- An FPGA Co-processor for Real-Time Visual Tracking.- Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware.- Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing.- Parallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform.- Crypto Applications 1.- Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2m).- 6.78 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm.- Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform.- A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation.- Keynote Address.- Creating a World of Smart Re-configurable Devices.- Multitasking.- Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs.- Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System.- Special Architectures.- The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance.- An FPGA Implementation of a Multi-comparand Multi-search Associative Processor.- Crypto Applications 2.- AES Implementation on FPGA: Time - Flexibility Tradeoff.- An FPGA Implementation of the Linear Cryptanalysis.- Compilation Techniques.- Compiling Application-Specific Hardware.- XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture.- Sea Cucumber: A Synthesizing Compiler for FPGAs.- DSP Applications 3.- Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs.- Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs.- High Performance Quadrature Digital Mixers for FPGAs.- Complex Applications.- HAGAR: Efficient Multi-context Graph Processors.- Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform.- On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach.- Architecture Implementation.- REFLIX: A Processor Core for Reactive Embedded Applications.- Factors Influencing the Performance of a CPU-RFU Hybrid Architecture.- Implementing Converters in FPLD.- A Quantitative Understanding of the Performance of Reconfigurable Coprocessors.- Design Flow.- Integration of Reconfigurable Hardware into System-Level Design.- A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures.- The Integration of SystemC and Hardware-Assisted Verification.- Using Design Hierarchy to Improve Quality of Results in FPGAs.- Miscellaneous.- Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations.- A General Hardware Design Model for Multicontext FPGAs.- Dynamically Reconfigurable Hardware — A New Perspective for Neural Network Implementations.- A Compilation Framework for a Dynamically Reconfigurable Architecture.- Short Papers.- Data Dependent Circuit for Subgraph Isomorphism Problem.- Exploration of Design Space in ECDSA.- 2D and 3D Computer Graphics Algorithms under MORPHOSYS.- A HIPERLAN/2 — IEEE 802.11a Reconfigurable System-on-Chip.- SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor.- Real-Time Medical Diagnosis on a Multiple FPGA-based System.- Threshold Element-Based Symmetric Function Generators and Their Functional Extension.- Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks.- Building Custom FIR Filters Using System Generator.- SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications.- Dynamic Constant Coefficient Convolvers Implemented in FPGAs.- VIZARD II: An FPGA-based Interactive Volume Rendering System.- RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing.- General Purpose Prototyping Platform for Data-Processor Research and Development.- High Speed Computation of Three Dimensional Cellular Automata with FPGA.- SOPC-based Embedded Smart Strain Gage Sensor.- Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications.- An FPGA-based Node Controller for a High Capacity WDM Optical Packet Network.- FPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms.- Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer.- A Novel Watermarking Technique for LUT Based FPGA Designs.- Implementing CSAT Local Search on FPGAs.- A Reconfigurable Processor Architecture.- A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor.- Gene Matching Using JBits.- Massively Parallel/Reconfigurable Emulation Model for the D-algorithm.- A Placement/Routing Approach for FPGA Accelerators.

Dettagli dell'edizione

• Editore: Springer Nature
• Data di pubblicazione: 2002
• Lingua: Inglese
• ISBN 10: 3540441085
• ISBN 13: 9783540441083
• Rilegatura: Copertina flessibile
• Numero di pagine: 1187
• Redattore: Zipf Peter, Renovell M.
• Contatto del produttore: non disponibile
• Persona responsabile: CMN Printpool Inh. Mathis Neumann; https://www.also.com/ec/cms5/en_6000/6000/index.jsp; ; Friedrich-Karl-Str. 9; Hamburg; Germania