Correct Hardware Design and Verification Methods: IFIP WG 10.2 Advanced Research Working Conference, CHARME'93, Arles, France, May 24-26, 1993. Proceedings: 683 - Brossura

Pierre, Laurence; Milne, George J.

Brossura

ISBN 10: 354056778X ISBN 13: 9783540567783

Casa editrice: Springer, 2008

Riassunto

These proceedings contain the papers presented at theAdvanced Research Working Conference on Correct HardwareDesign Methodologies, held in Arles, France, in May 1993,and organized by the ESPRIT Working Group 6018 CHARME-2andthe Universit de Provence, Marseille, in cooperation withIFIP Working Group 10.2.Formal verification is emerging as a plausible alternativeto exhaustive simulation for establishing correct digitalhardware designs. The validation of functional and timingbehavior is a major bottleneck in current VLSI designsystems, slowing the arrival of products in the marketplacewith its associated increase in cost. From being apredominantly academic area of study until a few years ago,formal design and verification techniques are now beginningto migrate into industrial use. As we are now witnessing anincrease in activity in this area in both academia andindustry, the aim of this working conference was to bringtogether researchers and users from both communities.

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Contenuti

A graph-based method for timing diagrams representation and verification.- A Petri Net approach for the analysis of VHDL descriptions.- Temporal analysis of time bounded digital systems.- Strongly-typed theory of structures and behaviours.- Verification and diagnosis of digital systems by ternary reasoning.- Logic verification of incomplete functions and design error location.- A methodology for system-level design for verifiability.- Algebraic models and the correctness of microprocessors.- Combining symbolic evaluation and object oriented approach for verifying processor-like architectures at the RT-level.- A theory of generic interpreters.- Towards verifying large(r) systems: A strategy and an experiment.- Advancements in symbolic traversal techniques.- Automatic verification of speed-independent circuit designs using the Circal system.- Correct compilation of specifications to deterministic asynchronous circuits.- DDD-FM9001: Derivation of a verified microprocessor.- Calculational derivation of a counter with bounded response time.- Towards a provably correct hardware implementation of occam.- Rewriting with constraints in T-ruby.- Embedding hardware verification within a commercial design framework.- An approach to formalization of data flow graphs.

Dettagli dell'edizione

• Editore: Springer
• Data di pubblicazione: 2008
• Lingua: Inglese
• ISBN 10: 354056778X
• ISBN 13: 9783540567783
• Rilegatura: Copertina flessibile
• Numero di pagine: 284
• Contatto del produttore: non disponibile
• Persona responsabile: CMN Printpool Inh. Mathis Neumann; https://www.also.com/ec/cms5/en_6000/6000/index.jsp; ; Friedrich-Karl-Str. 9; Hamburg; Germania