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Modeling and Synthesis of Behavior, Control and Data Flow.- 1 Introduction.- 2 Behavioral Synthesis.- 3 High-Level Control.- 4 Data Flow.- 5 Conclusion.- References.- Cell-based Logic Optimization.- 1 Introduction.- 2 Problem Formulation and Analysis.- 3 Algorithms for Library Binding.- 4 Boolean Matching.- 5 Generalized Matching.- 6 Conclusion.- References.- A Design Flow for Performance Planning: New Paradigms for Iteration Free Synthesis.- 1 Introduction.- 2 Flow Components.- 3 Layout Synthesis.- 4 Placement Versus Floorplan Design.- 5 Global Wires.- 6 Wire Planning.- 7 Gate Sizing.- 8 Conclusions.- References.- Test and Testable Design.- 1 Introduction.- 2 Defect Analysis and Fault Modeling.- 3 External Testing.- 4 Self-Testable Systems-On-Chip.- References.- Machine Assisted Verification.- 1 Introduction.- 2 Logic Verification.- 3 Bit-Vector and Word-Level Verification.- 4 Verification by Fixed-Point Calculations.- 5 Verification Techniques for Bounded State Sequences.- 6 Formally Correct Construction of Pipelined Systems.- References.- Models of Computation for System Design.- 1 Introduction.- 2 MOCs: Basic Concepts and the Tagged Signal Model.- 3 Common Models of Computation.- 4 Codesign Finite State Machines.- 5 Conclusions.- References.- Modular Design for the Java Virtual Machine Architecture.- 1 Introduction.- 2 The Trustful Virtual Machine.- 3 The Defensive Virtual Machine.- 4 The Diligent Virtual Machine.- 5 The Dynamic Virtual Machine.- 6 Related and Future Work.- 7 The JVM Abstract State Machine.
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