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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks
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PAP. Condizione: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Codice articolo L0-9783954040346
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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks
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PAP. Condizione: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Codice articolo L0-9783954040346
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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks
Da: California Books, Miami, FL, U.S.A.
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Condizione: New. Codice articolo I-9783954040346
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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks
Print on DemandDa: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Vertical integration of integrated circuit dies offers tremendous opportunities from an architectural as well as from an economical standpoint. Memory proximity supports performance scaling, and might enable significant energy savings. Partitioning of the corresponding functionalities and technologies into individual tiers can improve yield and modularity substantially.The paradigm change of stacking active components has a direct impact on heat-removal concepts and is therefore the motivation of this thesis. A stack comprised of a single logic layer in combination with multiple memory dies was identified as the limit for traditional back-side heat removal. To minimize junction temperatures, a stacking sequence with the high heat-flux component in close proximity to the cold plate is proposed.Interlayer cooling is the only volumetric heat-removal solution that scales with the number of dies in the stack. Hence, the focus of this thesis has been to identify the potential of interlayer cooling and to provide a modeling framework. Fundamental heat-transfer building blocks, such as unit-cell geometries, fluid structure modulation, fluid focusing, as well as four-port fluid delivery supporting power-map-aware heat removal, are discussed. Moreover, the theoretical foundation was experimentally validated on resistively heated convective test cavities. Therefore, specific bonding and insulation schemes were developed. Finally, the interlayer cooling performance was demonstrated on a pyramid chip stack. 172 pp. Englisch. Codice articolo 9783954040346
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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks
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Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Vertical integration of integrated circuit dies offers tremendous opportunities from an architectural as well as from an economical standpoint. Memory proximity supports performance scaling, and might enable significant energy savings. Partitioning of the corresponding functionalities and technologies into individual tiers can improve yield and modularity substantially.The paradigm change of stacking active components has a direct impact on heat-removal concepts and is therefore the motivation of this thesis. A stack comprised of a single logic layer in combination with multiple memory dies was identified as the limit for traditional back-side heat removal. To minimize junction temperatures, a stacking sequence with the high heat-flux component in close proximity to the cold plate is proposed.Interlayer cooling is the only volumetric heat-removal solution that scales with the number of dies in the stack. Hence, the focus of this thesis has been to identify the potential of interlayer cooling and to provide a modeling framework. Fundamental heat-transfer building blocks, such as unit-cell geometries, fluid structure modulation, fluid focusing, as well as four-port fluid delivery supporting power-map-aware heat removal, are discussed. Moreover, the theoretical foundation was experimentally validated on resistively heated convective test cavities. Therefore, specific bonding and insulation schemes were developed. Finally, the interlayer cooling performance was demonstrated on a pyramid chip stack. Codice articolo 9783954040346
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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks
Editore:
Jentzsch-Cuvillier, Annette, 2012
ISBN 10: 3954040344
ISBN 13: 9783954040346
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Da: moluna, Greven, Germania
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Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. KlappentextrnrnVertical integration of integrated circuit dies offers tremendous opportunities from an architectural as well as from an economical standpoint. Memory proximity supports performance scaling, and might enable significant energy sav. Codice articolo 119168031
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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks
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Taschenbuch. Condizione: Neu. Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks | Thomas Brunschwiler | Taschenbuch | Kartoniert / Broschiert | Englisch | 2012 | Cuvillier | EAN 9783954040346 | Verantwortliche Person für die EU: Cuvillier Verlag, Nonnenstieg 8, 37075 Göttingen, info[at]cuvillier[dot]de | Anbieter: preigu Print on Demand. Codice articolo 104317573
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