There is continuous research to exploit the improved speed of scaled CMOS technologies in realizing high-speed analog-to-digital converters and SAR ADCs are one of the candidates which can significantly benefit from this technology scaling. Remarkable improvements have been recently reported on single-channel time-interleaved charge-based SAR ADCs to achieve sampling rates in the range of GS/s with excellent power effeciency but the challenge of driving a large sampling capacitor with high accuracy in a short sampling window is often not addressed. In this work, a high-speed current-mode DAC is replacing the commonly used charge-mode SC-DAC which alleviates the problem of driving a large input sampling capacitor in a short time. The proposed current-mode SAR ADC also uses a Gm stage which converts the input voltage to a current which is then processed in a current-based binary search algorithm SAR loop. In comparison to the conventional SC-SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover, low-impedance DAC-reference voltages which are essential for SC-DAC are removed by using this approach.
Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -There is continuous research to exploit the improved speed of scaled CMOS technologies in realizing high-speed analog-to-digital converters and SAR ADCs are one of the candidates which can significantly benefit from this technology scaling. Remarkable improvements have been recently reported on single-channel time-interleaved charge-based SAR ADCs to achieve sampling rates in the range of GS/s with excellent power effeciency but the challenge of driving a large sampling capacitor with high accuracy in a short sampling window is often not addressed. In this work, a high-speed current-mode DAC is replacing the commonly used charge-mode SC-DAC which alleviates the problem of driving a large input sampling capacitor in a short time. The proposed current-mode SAR ADC also uses a Gm stage which converts the input voltage to a current which is then processed in a current-based binary search algorithm SAR loop. In comparison to the conventional SC-SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover, low-impedance DAC-reference voltages which are essential for SC-DAC are removed by using this approach. 132 pp. Englisch. Codice articolo 9786139928019
Quantità: 2 disponibili
Da: moluna, Greven, Germania
Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Elkafrawy AbdelrahmanDr.-Ing. Elkafrawy received his Ph.D. degree in mixed signal IC design from Institute of Microelectronics, University of Ulm, Germany, in 2016. His field of interests include mixed-mode amplifiers, LDOs, CLK buff. Codice articolo 385877710
Quantità: Più di 20 disponibili
Da: Revaluation Books, Exeter, Regno Unito
Paperback. Condizione: Brand New. 132 pages. 8.66x5.91x0.30 inches. In Stock. Codice articolo zk613992801X
Quantità: 1 disponibili
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germania
Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -There is continuous research to exploit the improved speed of scaled CMOS technologies in realizing high-speed analog-to-digital converters and SAR ADCs are one of the candidates which can significantly benefit from this technology scaling. Remarkable improvements have been recently reported on single-channel time-interleaved charge-based SAR ADCs to achieve sampling rates in the range of GS/s with excellent power effeciency but the challenge of driving a large sampling capacitor with high accuracy in a short sampling window is often not addressed. In this work, a high-speed current-mode DAC is replacing the commonly used charge-mode SC-DAC which alleviates the problem of driving a large input sampling capacitor in a short time. The proposed current-mode SAR ADC also uses a Gm stage which converts the input voltage to a current which is then processed in a current-based binary search algorithm SAR loop. In comparison to the conventional SC-SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover, low-impedance DAC-reference voltages which are essential for SC-DAC are removed by using this approach.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 132 pp. Englisch. Codice articolo 9786139928019
Quantità: 1 disponibili
Da: preigu, Osnabrück, Germania
Taschenbuch. Condizione: Neu. Concept and Design of a High Speed Current Mode Based SAR ADC | Abdelrahman Elkafrawy (u. a.) | Taschenbuch | 132 S. | Englisch | 2018 | LAP LAMBERT Academic Publishing | EAN 9786139928019 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Codice articolo 115056699
Quantità: 5 disponibili
Da: AHA-BUCH GmbH, Einbeck, Germania
Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - There is continuous research to exploit the improved speed of scaled CMOS technologies in realizing high-speed analog-to-digital converters and SAR ADCs are one of the candidates which can significantly benefit from this technology scaling. Remarkable improvements have been recently reported on single-channel time-interleaved charge-based SAR ADCs to achieve sampling rates in the range of GS/s with excellent power effeciency but the challenge of driving a large sampling capacitor with high accuracy in a short sampling window is often not addressed. In this work, a high-speed current-mode DAC is replacing the commonly used charge-mode SC-DAC which alleviates the problem of driving a large input sampling capacitor in a short time. The proposed current-mode SAR ADC also uses a Gm stage which converts the input voltage to a current which is then processed in a current-based binary search algorithm SAR loop. In comparison to the conventional SC-SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover, low-impedance DAC-reference voltages which are essential for SC-DAC are removed by using this approach. Codice articolo 9786139928019
Quantità: 1 disponibili
Da: Mispah books, Redhill, SURRE, Regno Unito
paperback. Condizione: New. NEW. SHIPS FROM MULTIPLE LOCATIONS. book. Codice articolo ERICA829613992801X6
Quantità: 1 disponibili