Advanced ASIC Chip Synthesis

Himanshu Bhatnagar

ISBN 10: 1475776292 / ISBN 13: 9781475776294

Editore: Springer US, Springer US Mai 2013, 2013

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Neuware -Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 360 pp. Englisch.

Codice articolo 9781475776294

Dati bibliografici

• Titolo: Advanced ASIC Chip Synthesis
• Editore: Springer US, Springer US Mai 2013
• Data di pubblicazione: 2013
• Lingua: Inglese
• ISBN 10: 1475776292
• ISBN 13: 9781475776294
• Rilegatura: Taschenbuch
• Condizione: Neu

Descrizione articolo

Riassunto

<em>Advanced ASIC Chip Synthesis: Using Synopsys® Design</em> <em>Compiler® Physical Compiler® and PrimeTime®, Second</em> <em>Edition</em> describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. <br> The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution. <br> Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.

Contenuti

Foreword. Preface. Acknowledgements. About the Author. 1. ASIC Design Methodology. 2. Tutorial. 3. Basic Concepts. 4. Synopsis Technology Library. 5. Partitioning and Coding Styles. 6. Constraining Designs. 7. Optimizing Designs. 8. Design for Test. 9. Links to Layout & Post Layout Opt. 10. Physical Synthesis. 11. SDF Generation. 12. Primetime Basics. 13. Static Timing Analysis. Appendix A. Appendix B. Index.