Advanced Formal Verification

Drechsler, Rolf (EDT)

ISBN 10: 1402077211 / ISBN 13: 9781402077210

Editore: Springer, 2004

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Codice articolo 2058585-n

Dati bibliografici

• Titolo: Advanced Formal Verification
• Editore: Springer
• Data di pubblicazione: 2004
• Lingua: Inglese
• ISBN 10: 1402077211
• ISBN 13: 9781402077210
• Rilegatura: Rilegato
• Condizione: New

Descrizione articolo

Riassunto

Advanced Formal Verification shows the latest developments in the verification domain from the perspectives of the user and the developer. World leading experts describe the underlying methods of today's verification tools and describe various scenarios from industrial practice. In the first part of the book the core techniques of today's formal verification tools, such as SAT and BDDs are addressed. In addition, multipliers, which are known to be difficult, are studied. The second part gives insight in professional tools and the underlying methodology, such as property checking and assertion based verification. Finally, analog components have to be considered to cope with complete system on chip designs.

Contenuti

Preface. Contributing Authors. Introduction; R. Drechsler. 1. Formal Verification. 2. Challenges. 3. Contributions to this Book. 1: What SAT-Solvers Can and Cannot Do; E. Goldberg. 1. Introduction. 2. Hard Equivalence Checking CNF Formulas. 3. Stable Sets of Points. 2: Advancements in Mixed BDD and SAT Techniques; G. Cabodi, S. Quer. 1. Introduction. 2. Background. 3. Comparing SAT and BDD Approaches: Are they Different? 4. Decision Diagrams as a Slave Engine in General SAT: Clause Compression by Means of ZBDDs. 5. Decision Diagram Preprocessing and Circuit-Based SAT. 6. Using SAT in Symbolic Reachability Analysis. 7. Conclusion, Remarks and Future Works. 3: Equivalence Checking of Arithmetic Circuits; D. Stoffel, E. Karibaev, I. Kufareva, W. Kunz. 1. Introduction. 2. Verification Using Functional Properties. 3. Bit-Level Decision Diagrams. 4. Word-Level Decision Diagrams. 5. Arithmetic Bit-Level Verification. 6. Conclusion. 7. Future Perspectives. 4: Application of Property Checking; R. Brinkmann, P. Johannsen, K. Winkelmann. 1. Circuit Verification Environment: User's View. 2. Circuit Verification Environment: Underlying Techniques. 3. Exploiting Symmetries. 4. Automated Data Path Scaling to Speed Up Property Checking. 5. Property Checking Use Cases. 6. Summary. 5: Assertion-Based Verification; C.N. Coelho Jr, H.D. Foster. 1. Introduction. 2. Assertion Specification. 3. Assertion Libraries. 4. Assertion Simulation. 5. Assertions and Formal Verification. 6. Assertions and Synthesis. 7. PCI Property Specification Example. 8. Summary. 6: Formal Verification for Nonlinear Analog Systems; W. Hartong, R. Klausen, L. Hedrich. 1. Introduction. 2. System Description. 3. Equivalence Checking. 4. Model Checking. 5. Summary. 6. Acknowledgement. Appendix: Mathematical Symbols. Index.