Analysis and Design of CMOS Clocking Circuits for Low Phase Noise

Woorham Bae

ISBN 10: 1785618016 / ISBN 13: 9781785618017

Editore: Institution Of Engineering & Technology Aug 2020, 2020

Riguardo questo articolo

Neuware - As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances.

Codice articolo 9781785618017

Dati bibliografici

• Titolo: Analysis and Design of CMOS Clocking Circuits for Low Phase Noise
• Editore: Institution Of Engineering & Technology Aug 2020
• Data di pubblicazione: 2020
• Lingua: Inglese
• ISBN 10: 1785618016
• ISBN 13: 9781785618017
• Rilegatura: Buch
• Condizione: Neu
• Dimensioni: 239 L x 157 A x 18 P (millimetri) 239 millimetri di larghezza per 157 millimetri di altezza per 18 millimetri di profondità
• Peso: 567 grammi

Descrizione articolo

Riassunto

As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances, making it a useful guide for newcomers to the field, and offering an opportunity for established researchers to broaden and update their knowledge of current trends.

The book begins by introducing the theory of Fourier transform and power spectral density, then builds on this foundation in chapter 2 to define phase noise and jitter. Chapter 3 discusses the theory and primary implementation of CMOS oscillators, including LC oscillators and ring oscillators, and chapter 4 introduces techniques for analysing their phase noise and jitter. Chapters 5-7 cover conventional clocking circuits; phase-locked loop (PLL) and delay-locked loop (DLL), which suppress the phase noise of CMOS oscillators. The building blocks of conventional PLLs/DLLs are described, and the dynamics of the PLL/DLL negative feedback loop explored in depth, with practical design examples. Chapters 8-11 address state-of-the-art circuit techniques for phase noise suppression, presenting the principles and practical issues in circuit implementation of sub-sampling phase detection techniques, all-digital PLL/DLL, injection-locked oscillator, and clock multiplying DLL. Extensive survey and discussion on state-of-the-art clocking circuits and benchmarks are covered in an Appendix.