Applications of VHDL to Circuit Design

Harr, Randolph E.; Stanculescu, Alec G.

ISBN 10: 0792391535 / ISBN 13: 9780792391531

Editore: Kluwer Academic (edition 1991), 1991

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Codice articolo 0792391535-11-1

Dati bibliografici

• Titolo: Applications of VHDL to Circuit Design
• Editore: Kluwer Academic (edition 1991)
• Data di pubblicazione: 1991
• Lingua: Inglese
• ISBN 10: 0792391535
• ISBN 13: 9780792391531
• Rilegatura: Hardcover
• Edizione: 1991.
• Condizione: Good

Descrizione articolo

Riassunto

Describing and designing complex electronic systems has become an overwhelming activit)' for which VHDL is showing increasingly useful and promising support. Although created as a description language. VHDL is being increasingly used as a simulatable and synthcsizablcdcsign language. For the first time, here is abook which describesa number of unique and powerful ways VHDL can be used to solve typical design problems in systems •• ones which must be designed correctly in vcry short periodsoflime. Typically useful lcchniquessuch as switch-level modeling, mixed analog and digital modelling, and advanced synthesis for which VHDL showsgrealpromisearefully presented. Thesemeth· ods are bOlh immedial.ely applicable. and indicale lIle potential of VHDL in efficiently modelling Ihe real worldofelectronic systems. Sinceitsinception.there hasbeen adesireforananalogdescription languageconsistent with (and integrated with) VHDL. Until recently. VHDL could onl)' be applied to digital circuits.ootlhedreamofdescribingandsimulatingmixedanalogand digitalcircuitsis now a reality as described herein. Describing the functionality of analog circuits including intetoperability with digital circuits using the VHDL paradigm is surprisingly easy and powerful. The approach outlined by the authors presages a significant advance in the simulation of mixed systems.

Contenuti

1. Switch-Level Modeling in VHDL.- 1.1 Introduction.- 1.1.1 Overview.- 1.1.2 Why Switch-level VHDL Descriptions.- 1.1.3 A Switch-level Modeling Solution in VHDL.- 1.1.4 Choice of Algorithm: Interpretative vs. Compiled, and Global vs. Distributed.- 1.2 Advanced Simulator Programming.- 1.2.1 VHDL Simulation Cycle.- 1.2.2 Variables vs Signals & Predefined Attributes.- 1.2.3 Concurrent vs. Sequential Statements.- 1.2.4 User-defined Packages.- 1.2.5 User-defined Types l.- 1.2.6 Value-System and Resolution Functions.- 1.2.7 Properties of Resolution Functions.- 1.3 Switch-Level Package.- 1.3.1 46-value System.- 1.3.2 Functional Support for the 46-value System.- 1.4 Distributed Algorithm for Pass-transistor.- 1.4.1 Modeling Assumptions.- 1.4.2 Overview of Algorithm.- 1.4.3 Completion of Distributed Algorithm.- 1.5 VHDL Implementation of Distributed Algorithm.- 1.6 Examples of Switch-level Networks.- 1.6.1 One-bit RAM.- 1.6.2 Memory Cell based on two Inverters.- 1.6.3 1,2,4 and 6-bit adders.- 1.6.4 Performance of VHDL Switch-level simulation.- 1.7 Future Research.- 1.7.1 Transistor-network Pattern Recognition.- 1.7.2 More Complex Value-System.- 1.7.3 Hardwired Implementations.- 1.7.4 Analog Models in VHDL.- 1.8 Conclusion.- 1.9 References.- 2. Modeling of Transmission Line Effects in Digital Circuits.- 2.1 Introduction.- 2.2 Underlying Concepts and Structure.- 2.2.1 Superposition.- 2.2.2 Identifying and Structuring Modeling Information.- 2.2.3 General Model Structure.- 2.3 Behavioral Models.- 2.3.1 Losstess Transmission Line.- 2.3.2 Receiver.- 2.3.3 Linear Driver.- 2.3.4 General Driver.- 2.4 Application of Transmission Line Behaviors.- 2.4.1 FET Modeling with the General Driver Model.- 2.4.2 Network Example.- 2.4.3 Simulation Results.- 2.4.4 Limitations and Usage.- 2.5 Summary.- References.- 3. Behavior Modeling of Mixed Analog-Digital Circuits.- 3.1 Introduction.- 3.2 Simulation Model.- 3.2.1 Theory.- 3.2.2 General Model Structure.- 3.2.3 Application to Circuits.- 3.3 Design Verification Methodology.- 3.3.1 Step 1: Cell Level.- 3.3.2 Step 2: Chip Level.- 3.4 Application of Analog-Digital Behaviors.- 3.4.1 Function Generator Model.- 3.4.2 Receiver Model.- 3.4.3 Network Example.- 3.4.4 Simulation Results.- 3.4.5 Limitations.- 3.4.6 Model Usage.- 3.5 Summary.- References.- 4. Modeling of Analog-Digital Loops in VHDL.- 4.1 introduction.- 4.2 AGC Loop Behavioral Models.- 4.2.1 Variable Gain Amplifier.- 4.2.2 Envelope Detector.- 4.2.3 Integrating Capacitor.- 4.3 Application of Automatic Gain Control Loops.- 4.3.1 Network Example.- 4.3.2 Simulation Results.- 4.4 Phase-Locked Loop Behavioral Models.- 4.4.1 Single Shot.- 4.4.2 Phase/Frequency Detector.- 4.4.3 Charge Pump.- 4.4.4 Second-Order Filter.- 4.4.5 Voltage Controlled Oscillator.- 4.5 Application of Phase-Locked Loop.- 4.5.1 Network Example.- 4.5.2 Simulation Results.- 4.5.3 Limitations and Usage.- 4.6 Summary.- References.- 5. Modeling Style Issues for Synthesis.- 5.1 What is HDL Synthesis?.- 5.2 Applying HDL Synthesis Technology.- 5.2.1 The Synthesis Continuum.- 5.2.2 Quality/Productivity Design Automation Acceptance Criteria.- 5.2.3 Practical Considerations.- 5.3 An HDL Synthesis Policy.- 5.3.1 Design Methodology.- 5.3.2 Design Style.- 5.3.3 Supported Language Constructs.- 5.4 Synthesis of Register Transfer Level Constructs.- 5.5 Synthesis Style Issues in VHDL.- 5.5.1 Process Independent Modeling Paradigm.- 5.5.2 Synchronous Operation Through Implicit Storage Elements.- 5.5.3 Partially Asynchronous Operation.- 5.5.4 Asynchronous Operation.- 5.6 A Complete Example.- 5.7 Closing Remarks.- 6. Modeling of Standard Component Libraries.- 6.1 Structure of Model Libraries.- 6.2 Relevant Issues in Logic Simulation.- 6.3 Layers of Abstraction.- 6.4 Independence from Physical Packaging.- 6.5 Strength/Level Values Set Independence.- 6.6 Independence from Timing Parameter Values.- 6.7 Toward a Standard.- 6.8 Summary.- 7. Anomalies in VHDL and How to Address Them.- 7.1 Common Misconceptions about VHDL.- 7.1.1 VHDL Processes and Drivers.- 7.1.2 Initialization of Signals.- 7.1.3 Working Around the Lack of Global Variables in VHDL.- 7.1.4 Use of ‘out’ and ‘buffer’ Mode Ports.- 7.1.5 Use of Bus and Register Signals.- 7.1.6 Predefined Signal Attributes.- 7.2 VHDL Language Inconsistencies.- 7.2.1 The Textio Package.- 7.2.2 Spaces in Abstract/Physical Literals.- 7.2.3 Null Slices.- 7.2.4 Slices in Case Statements.- 7.2.5 Resolution Function Parameters.- 7.3 Summary.- 7.4 References.