Architecting the Modern VLSI Chip: Semiconductor Devices, CMOS, RTL, Physical Design, and Tape-Out (Modern Semiconductor Design and Computing Architecture)

A modern chip is not designed in one discipline. It is negotiated across an entire chain of constraints.

A transistor decision can become a timing problem.
A timing decision can become a routing problem.
A routing decision can become a power-integrity problem.
And a design that works perfectly in simulation can still fail when geometry meets silicon.

Architecting the Modern VLSI Chip was written to show you that entire chain.

Instead of treating semiconductor physics, CMOS, RTL, synthesis, timing analysis, physical design, verification, manufacturing, and packaging as isolated subjects, this book connects them into one continuous engineering system.

The goal is not simply to know what each stage does. It is to understand what happens next when you change something now.

Beginning with the physical limits of semiconductor devices, the book follows the design forward through CMOS circuits and interconnect, RTL and synthesis, static timing analysis, placement and routing, physical verification, fabrication constraints, sign-off, and tape-out.

Then it goes further.

You will examine:

• Semiconductor devices, MOSFET behaviour, FinFETs, gate-all-around and nanosheet technologies
• Interconnect resistance, capacitance, crosstalk, IR drop and electromigration
• CMOS logic, standard cells, SRAM and SPICE simulation
• RTL architecture and synthesizable SystemVerilog
• Logic synthesis, SDC constraints and static timing analysis
• Setup, hold, clock skew, variation and timing closure
• Floorplanning, placement, clock-tree synthesis and routing
• EUV lithography, parasitic extraction, DRC, LVS and manufacturing sign-off
• Functional verification, UVM, assertions, formal methods and emulation
• Scan, ATPG, BIST, JTAG and post-silicon debug
• Clock gating, power gating, DVFS, UPF and thermal design
• Reliability, aging, ESD, soft errors and functional safety
• Analog, mixed-signal, PLL, ADC/DAC and high-speed SerDes design
• SoC architecture, RISC-V, memory systems, networks-on-chip and AI accelerators
• Chiplets, 2.5D/3D integration, HBM, UCIe and advanced packaging
• Hardware security, side-channel attacks, fault injection and roots of trust
• AI-assisted EDA, machine-learning-driven optimization and open-source flows including Yosys, OpenROAD and Verilator

But the real value is in the connections between them.

Why does a device-level physical effect appear later as a timing failure?

Why can an architectural decision become a congestion problem during physical design?

Why can apparently clean RTL still produce an implementation that cannot meet power, timing or manufacturing constraints?

These are the questions that separate knowing individual tools from understanding chip design as a system.

Architecting the Modern VLSI Chip builds that systems-level view.

It is written for engineers, electronics and computer-engineering students, chip designers, technically serious readers, and anyone who wants to understand how an idea progresses from physical device behaviour to a controlled design database ready for fabrication.

The book can be read sequentially as a complete VLSI design journey or used as a technical reference when you need to move between abstraction levels.

From transistor physics to tape-out, this is the map of how the modern chip actually comes together.